Publications
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, “Using synchronized oscillators to compute the maximum independent set”, Nature Communications, 2020.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range”, IEEE Solid-State Circuits Letters (SSCL), 2020.
A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB), “A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber”, in IEEE International Solid-State Circuits Conference (ISSCC), 2023. 15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB)
15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB), “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling”, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022. NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB), “Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance”, Journal of Applied Physics, 2018.
, “Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020. Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB), “ISPI: A 2-Wire Improved Serial Peripheral Interface with Automatic Routing Algorithm for 2-D In-Textile Distributed Computing and Storage Systems”, in 2025 IEEE Custom Integrated Circuits Conference (CICC) , 2025.
, “Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
, “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “Graph Coloring using Coupled Oscillator-based Dynamical Systems”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
, “A Fully Integrated, Custom End-to-End PPG Sensing System for Ultra-Low Power Wearables”, in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), In Press.
, “A Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packets”, IEEE Journal of Solid-State Circuits, 2021.
, “A Crystal-Less BLE Transmitter with -86dBm Frequency-Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “A Cooperative 0.6×1.2mm Fully On-chip Switched-Capacitor Voltage Regulator with Communication-free Multi-chip Output Voltage Matching for Distributed Power Management in Networks-on-Textiles”, in 2025 IEEE European Solid-State Electronics Research Conference (ESSERC), In Press.
, “A comprehensive analysis of Auger generation impacted planar Tunnel FETs”, Solid-State Electronics, 2020.
, “Characterization of Stacked PV Cell Configurations in a Deep N-Well 65nm CMOS Technology”, in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), In Press.
, “Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
, “Auger Effect Limited Performance in Tunnel Field Effect Transistors”, in 5th Berkeley Symposium on Energy Efficient Electronics & Steep Transistors Workshop, Berkeley, CA, 2017.
, “An 81.0% Peak Efficiency, 1.0W/cm^3 Miniaturized 5V/1A AC-DC Converter using a Highly-Integrated Primary-Side Active Clamp Flyback Controller with Adaptive Frequency and Zero-Voltage Switching”, in 2025 IEEE Custom Integrated Circuits Conference (CICC), 2025.
, “A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic”, IEEE Solid-State Circuits Letters (SSCL), 2019. A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB), “A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)
A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB), “A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution”, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019. A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB), “A 33nW Fully Autonomous SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for mm-scale System-in-Fiber”, in IEEE Transactions on Biomedical Circuits and Systems, Invited paper, 2023. A_33nW_Fully_Autonomous_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_mm-scale_System-in-Fiber.pdf (16.09 MB)
A_33nW_Fully_Autonomous_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_mm-scale_System-in-Fiber.pdf (16.09 MB), “A 2-Dimensional mm-scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6mm x 2.15mm SoC and bySPI chiplets”, in 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025.