This paper investigates the effect of body biasing on the leakage and delay of dynamic leakage suppression (DLS) logic. We present a brief theoretical analysis of the impact of body biasing on DLS logic as well as measurements from a test chip in 65nm CMOS. Results show that forward body biasing can reduce delay by up to 41X with negligible impacts on leakage.
This letter presents an energy efficient, temperature-compensated frequency-locked loop (FLL) for use as an on-chip clock source. We first present a fully integrated FLL architecture that significantly improves energy efficiency by using a loop divider to boost the output frequency without requiring increased static power dissipation. We develop models for the FLL energy-per-cycle and temperature stability and use them to implement an energy-optimized and highly temperature-stable FLL design in 65-nm CMOS that achieves 20.3-ppm/◦C temperature stability from −20 ◦C to 60 ◦C and an energy efficiency of 44.6-fJ/cycle at 23 ◦C (45.3 nW at 1.016 MHz), which is the highest energy efficiency reported to date for a fully on-chip oscillator, regardless of architecture, operating frequency, or temperature stability.
A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic
A 256kb 6T Self-Tuning SRAM with Extended 0.38V-1.2V Operating Range using Multiple Read/Write Assists and VMIN Tracking Canary Sensors
A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications
A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic