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In this work, we evaluate the impact of different peripheral write assist techniques, since the write operation limits voltage scaling, on the stability and energy of complete SRAM arrays operating in the sub-threshold region. The results of this characterization show that the best choice for a supply voltage and write assist combination varies based on the system level constraints and objectives. |
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In this paper, we propose a 9T half-select-free subthreshold bitcell that has 2.05X lower mean read energy, 12.39% lower mean write energy, and 28% lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors. |
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This work shows a closed loop self-tuning 256kb 6T SRAM with super-threshold to sub-threshold 0.38V-1.2V extended operating range using combined read and write assists and in-situ dynamic VMIN tracking canary sensors. A 337X power reduction is achieved using multiple combined peripheral assists and an additional and 4.3X power reduction is achieved using VMIN tracking canary sensors that removes the VMIN guardbanding, respectively. Combining both methods saves 1444X in active power and 12.4X in leakage at the 0.38V.. |
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In this paper, we show the first silicon results of a working 512b canary SRAM using reverse assist in 130nm bulk technology which can be tuned to fail earlier than the 8Kb SRAM fails by tuning the bitline or wordline type reverse assists. We further show that this tuning is possible across voltage, frequency, and temperature variations. We report that the 512b canary SRAM has 60% less power consumption than the 8Kb SRAM at 100MHz. |
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This work compares six different 8T SRAM bitcells targeting different design space requirements - such as reliability and low power/energy - for Internet of Things (IoT) applications. Different bitcells leverage the varying characteristics of high threshold (high-VT) and standard-threshold (standard-VT) devices to affect SRAM metrics like write margin (WM), Data Retention Voltage (DRV), Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM), write and read energy, standby leakage power, and variability. The reliability for each bitcell over process (intra- and inter-die variation) and temperature variation is also evaluated. Measured results for a commercial 130nm test chip compare the most promising two 8T bitcell structures targeting low leakage and low energy. |
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ViPro for Register Files (RFs) - not only explores methodologies of designing low power and high performance RFs and it also extends a virtual prototyping (ViPro) tool to support fast and efficient estimation of different design knobs on the overall multi-port RF macros. The extension of ViPro fills the blank of the multi-port register files, and provides hierarchical BL scheme as an extra knob for better memory design.
Similar tool likes CACTI developed by HP Laboratories also evaluates delay and energy of memories, but the results are extremely inaccurate due to using a mathematical circuit model. The left figure above illustrates the delay and energy of a gate chain which is a fundamental element of circuits, and results of CACTI using high performance and low power transistors are both substantially different from SPICE simulation results of the commercial technology and the predictive technology model for the same gate chain.
The right figure above shows the Pareto curves of the 8T 1R/1W bitcell with single-ended BL sensing, differential BL sensing, and two hierarchical BL (16bits/LBL & 32bits/LBL) sensing schemes at 8KB capacity. Two hierarchical BL sensing schemes contribute to the combined Pareto curve.
