|Enabling self-powered in-fiber or in-textile sensing systems necessitates the development of a compact, highly expandable, and ultra-low-power (ULP) communication protocol. This work presents an ULP “bypass-SPI” chip-to-chip interconnect bus designed specifically for fabric-based network communication, requiring only a fixed set of four wires. This interconnect bus allows the chips to bypass the interconnect signals to the downstream chips using a dedicated bypass procedure, facilitating small form factors. A voltage and direction controller is integrated on-chip, which allows the expansion of interconnect signals in multiple directions, supporting mesh-style distributed fiber networks and enabling voltage shifting. Moreover, this interconnect bus is synthesizable, compatible with the standard SPI interfaces, and can be converted into an I2C protocol, significantly improving its flexibility. Fabricated in 65nm CMOS technology, measurements of the chip show that the chip achieves a minimum standby power of 2.3 nW and reduces the energy per cycle by over 17× down to 1 pJ/bit, compared to prior art. The communication between bypass-SPI chips and a RISC-V SoC is also measured, confirming the suitability of this interconnect bus for energy-and-space-constrained fabric-based sensing applications.
Energy Efficient Circuit Design
This work presents an implementation of a 16-bit MSP430 processor for ultra-low-power (ULP) systems catering to battery-less wireless sensor nodes, biomedical, and other IoT applications. Implemented in a custom extremely low power (xLP) 90nm FDSOI process, the processor consumes 1.3μW operating at 0.4V while executing a peak detection algorithm at 250 kHz. It supports the standard MSP430 instruction set architecture (ISA) and demonstrates QRS peak detection for an Electrocardiogram (ECG) application. The measured energy while executing peak detection at 250 kHz was 5pJ per cycle at 0.4V. The fabricated xLP devices show 55% reduction in threshold voltage (Vth) variation compared to similar-sized transistors in a traditional FDSOI process.
As energy-constrained systems continue to reduce their power consumption, finding an optimal point of operation for the principle components in the energy budget becomes increasingly important. With energy dominant system components like communication circuits, it is important to consider both energy-per-bit and power in the context of the system’s use cases. In this project, we propose optimization of chip-to-chip links considering both power and energy per-bit to find the optimal operating voltage and activity factor while minimizing wasted energy and power.
This work explores reconfigurable circuits operating at low voltages. While the existing FPGAs are too high power to meet the requirements of IoT applications, we designed and optimized new circuit typologies of CLBs and global interconnect in near/sun-threshold region. We also developed custom tool flow to support full chip configuration. A 90nm chip implements the FPGA with 1134 LUTs, which is 2.7X smaller, 14X faster, and 4.7X less energy than a sub-threshold FPGA using conventional circuits and 22X less energy than an equivalent FPGA at full VDD. We are currently working towards dynamic voltage scaling and measurements using real-life applications.