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Wake-Up Receiver

Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver

A -108dBm sensitivity, 430MHz, 130nW-41µW, 6.25bps-4.2kbps, digitally tunable wake-up and data receiver in 65nm CMOS is presented. Employing 2-tone RF OOK modulation and an AlN MEMS resonator, the receiver attains close-in SIR of -25dB at 0.12% and far-out SIR of -28dB at 0.7% frequency offset from the carrier. Digitally configurable dynamic ranges of 11dB, 410X, 672X are achieved for sensitivity, power, and latency, respectively. The design receives data at a 4.2kbps bit-rate at - 108dBm sensitivity while consuming 41µW. The proposed WuRx is a highly reconfigurable and interference robust candidate for emerging ultra-long range IoT LPWAN applications.


Within-Packet Duty-Cycled Wake-Up Receiver

This work presents a highly integrated 2.4-GHz wake-up receiver (WuRX) achieving 91.5 dBm sensitivity with a state-of-the-art power and latency combination of 2 µW at 100 ms. The proposed within-packet duty-cycling method employs a carrier-sense mechanism to turn off the WuRX early under idle channel conditions, which reduces the dc-power compared with conventional asynchronous packet-level duty cycling by 9× at 10 ms latency (21 µW) and 2× at 1 s latency (0.9 µW) at the cost of 2 dB in sensitivity. The uncertain-IF topology with a phase-locked loop (PLL)-aided event-driven calibrated local-oscillator (LO) helps reduce the dc-power while maintaining a fast startup. The channel-embedded OOK scheme is used to create a deterministic IF to enable baseband (BB) channel selection and achieve continuous wave (CW) interference tolerance of −47 dB at 20 MHz offset. Fabricated in 65 nm CMOS, input matching and LC oscillator are all implemented on-chip, and operation is demonstrated with integrated low dropout regulators to capture the degradations in realistic system integration.
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