Publications
] , โUltra-Dynamic Voltage Scaling for Energy Starved Electronicsโ, in Proc. of GOMAC Tech, 2007.
, โAn Enhanced Adaptive Canary System for SRAM Standby Power Reductionโ, in TECHCON, 2008.
, Sub-threshold Design for Ultra Low-Power Systems. Springer, 2006.
, โTwo Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMsโ, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.
, โA 2.3-5.7ฮผW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2 , and Pulse Transit Time Co-Monitoringโ, IEEE Transactions on Biomedical Circuits and Systems, 2024.
, โTechniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyondโ, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.
, โA 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoringโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, โStatistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Arrayโ, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
, โA 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25ยฐC Resolutionโ, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019.
A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB), โA 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/ยฐC Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loopโ, IEEE Journal of Solid-State Circuits, 2021. A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)
A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB), โImproving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOSโ, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
, โNanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scalingโ, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022. NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB), โChannel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuitsโ, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
, โMinimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETsโ, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020. Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB), โA 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/ยฐC Stability Using a Duty-Cycled Digital Frequency-Locked Loopโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB), โA 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/ยฐC Stabilityโ, IEEE Solid-State Circuits Letters (SSCL), 2019. A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB), โA 6โ140-nW 11 Hzโ8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logicโ, IEEE Solid-State Circuits Letters (SSCL), 2019. A 6โ140-nW 11 Hzโ8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
A 6โ140-nW 11 Hzโ8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB), โA Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Rangeโ, IEEE Solid-State Circuits Letters (SSCL), 2020. A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB), โReducing the Cost of Safety-Critical Systems with On-Demand Redundancyโ, in SRC Techcon, 2012.
, โA Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensingโ, in IEEE Sensors, 2010.
, โFast Algorithm for Clock Grid Simulationโ, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
, โRecursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Designโ, in International Conference on VLSI Design, India, 2008, pp. 131-136.
, โA 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systemsโ, in EEE International Solid-State Circuits Conference (ISSCC), 2015.
, โA Charge Pump Based Receiver Circuit for a Voltage Scaled Interconnectโ, in International Symposium on Low Power Electronics and Design, 2012.