Publications
] , โA 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Nodeโ, in VLSI Design Conference, 2013.
, โA 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCsโ, in Custom Integrated Circuits Conference, San Jose, 2012.
, โRecursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Designโ, in International Conference on VLSI Design, India, 2008, pp. 131-136.
, โFast Algorithm for Clock Grid Simulationโ, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
, โA Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensingโ, in IEEE Sensors, 2010.
, โReducing the Cost of Safety-Critical Systems with On-Demand Redundancyโ, in SRC Techcon, 2012.
, โA 6โ140-nW 11 Hzโ8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logicโ, IEEE Solid-State Circuits Letters (SSCL), 2019.
A 6โ140-nW 11 Hzโ8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
A 6โ140-nW 11 Hzโ8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB), โA Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Rangeโ, IEEE Solid-State Circuits Letters (SSCL), 2020. A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB), โA 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25ยฐC Resolutionโ, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019. A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB), โA 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/ยฐC Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loopโ, IEEE Journal of Solid-State Circuits, 2021. A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)
A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB), โImproving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOSโ, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
, โNanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scalingโ, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022. NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB), โChannel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuitsโ, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
, โMinimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETsโ, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020. Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB), โA 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/ยฐC Stability Using a Duty-Cycled Digital Frequency-Locked Loopโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB), โA 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/ยฐC Stabilityโ, IEEE Solid-State Circuits Letters (SSCL), 2019. A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB), โA 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoringโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, โStatistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Arrayโ, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
, โCanary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAMโ, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.
, โStandby Supply Voltage Minimization for Reliable Nanoscale SRAMsโ, in Solid State Circuits Technologies, INTECH, 2010.
, โMinimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variationsโ, Transactions on VLSI Systems (TVLSI), 2011.
, โDark vs. Dim Silicon and Near-Threshold Computingโ, in Dark Silicon Workshop (DaSi), 2012.
, โImproving SRAM Vmin and Yield by Using Variation-Aware BTI Stressโ, in CICC, San Jose, CA, 2010.
, โAn Enhanced Canary-based System with BIST for SRAM Standby Power Reductionโ, Transactions on VLSI Systems (TVLSI), 2011.
, โAnalyzing Static and Dynamic Write Margin for Nanometer SRAMsโ, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.