Publications
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Filters: Author is Benton H. Calhoun [Clear All Filters]
“Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
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“A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, “A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range”, IEEE Solid-State Circuits Letters (SSCL), 2020.
A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
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“Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations”, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper), 2020.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “Using synchronized oscillators to compute the maximum independent set”, Nature Communications, 2020.
, “A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability”, IEEE Solid-State Circuits Letters (SSCL), 2019.
A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
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“A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time”, IEEE Journal of Solid-State Circuits (JSSC), 2019.
, “A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution”, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019.
A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
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“A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic”, IEEE Solid-State Circuits Letters (SSCL), 2019.
A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
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“A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×105 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple”, in IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, 2019.
, “A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications”, in 32nd International Conference on VLSI Design, 2019.
, “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
, “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated Maximum-Power-Point Tracking”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis”, Journal of Low Power Electronics and Applications (JLPEA), 2018.
, “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
, “A 486 µW All-Digital Bluetooth Low Energy Transmitter with Ring Oscillator Based ADPLL for IoT applications”, in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018.
, “A -76dBm 7.4 nW wakeup radio with automatic offset compensation”, in International Solid-State Circuits Conference (ISSCC), 2018.
, “Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
, “FGC: A Tool-flow for Generating and Configuring Custom FPGAs”, Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, Monterey, CA, 2018.
, “Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance”, Journal of Applied Physics, 2018.
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