VLSI Design Group

Navigation

Search This Site

Publications

2014
J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications, in GOMAC Tech, 2014.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., Modeling SRAM Dynamic VMIN, in International Conference on IC Design and Technology (ICICDT), 2014.
S. Khanna, Nalam, S. V., and Calhoun, B. H., Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories, in VLSI Design Conference, 2014.
A. Klinefelter and Calhoun, B. H., A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs, in S3S Conference, Monterey, CA, 2014.
A. Banerjee, Sinangil, M., Poulton, J., Gray, C. T., and Calhoun, B. H., A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs, in International Symposium on Quality Electronic Design (ISQED), 2014.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM, in Design Automation Conference (DAC), 2014.
A. Banerjee and Calhoun, B. H., An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
2013
N. Gilbert, Zhang, Y., Dinh, J., Calhoun, B., and Hollmer, S., A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications, in Symposium on VLSI Circuits, 2013.
A. Shrivastava, Pandey, J., Otis, B., and Calhoun, B. H., A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node, in VLSI Design Conference, 2013.
Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.
A. Shrivastava and Calhoun, B. H., A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications, 2013.
P. Beshay, Ryan, J. F., and Calhoun, B. H., A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers, Journal of Low Power Electronics and Applications, 2013.
C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae, PLOS One, vol. Vol. 8, No. 7, 2013.
Y. Zhang and Calhoun, B. H., Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method, in S3S Conference, Monterey, California, 2013.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B., Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN, in Design Automation and Test Europe, 2013.
A. Banerjee and Calhoun, B. H., An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell, in S3S, Monterey, CA, 2013.
J. Boley, Beshay, P., and Calhoun, B., Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization, in SRC TECHCON, 2013.
2012
A. Shrivastava and Calhoun, B. H., A 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCs, in Custom Integrated Circuits Conference, San Jose, 2012.
J. Boley, Wang, J., and Calhoun, B. H., Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin, Journal of Low Power Electronics and Applications, 2012.
J. Boley, Wang, J., and Calhoun, B. H., Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.
F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC, in ISSCC, San Francisco, 2012.
A. Shrivastava, Lach, J., and Calhoun, B., A Charge Pump Based Receiver Circuit for a Voltage Scaled Interconnect, in International Symposium on Low Power Electronics and Design, 2012.
Y. Shakhsheer, Zhang, Y., Otis, B., and Calhoun, B. H., A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS, Custom Integrated Circuits Conference. San Jose, 2012.
L. Wang, Skadron, K., and Calhoun, B. H., Dark vs. Dim Silicon and Near-Threshold Computing, in Dark Silicon Workshop (DaSi), 2012.
B. H. Calhoun, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.

Pages