Robust Low Power VLSI
VLSI Design Group

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Publications

2018
D. S. Truesdell and Calhoun, B. H., “Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
O. Ayorinde, Qi, H., and Calhoun, B. H., “FGC: A Tool-flow for Generating and Configuring Custom FPGAs”, Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, Monterey, CA, 2018.
H. L. Bishop, Wang, P., Fan, D., Lach, J., and Calhoun, B. H., “Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems”, in Global Internet of Things Summit (GIoTS), 2018.
S. Z. Ahmed, Tan, Y., Truesdell, D. S., Calhoun, B. H., and Ghosh, A., “Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance”, Journal of Applied Physics, 2018.
A. Banerjee, Kamineni, S., and Calhoun, B. H., “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
D. Akella Kamakshi, Guo, X., Patel, H. N., Stan, M. R., and Calhoun, B. H., “A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs”, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things”, Journal of Low Power Electronics & Applications, 2018.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., “An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches”, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
2017
A. Banerjee, Liu, N., Patel, H. N., and Calhoun, B. H., “A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors”, in 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, 2017.
J. Breiholz, Yahya, F., Lukas, C. J., Chen, X., Leach, K., Wentzloff, D., and Calhoun, B. H., “A 4.4 nW Lossless Sensor Data Compression Accelerator for 2.9x System Power Reduction in Wireless Body Sensors”, in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 2017.
A. Roy and Calhoun, B. H., “A 71% Efficient Energy Harvesting and Power Management Unit for Sub-µW Power Biomedical Applications”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
S. Z. Ahmed, Tan, Y., Truesdell, D. S., and Ghosh, A., “Auger Effect Limited Performance in Tunnel Field Effect Transistors”, in 5th Berkeley Symposium on Energy Efficient Electronics & Steep Transistors Workshop, Berkeley, CA, 2017.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., “Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems”, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
H. N. Patel, Mann, R. W., and Calhoun, B. H., “Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications”, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
H. N. Patel, Yahya, F. B., and Calhoun, B. H., “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
H. Qi, Ayorinde, O., and Calhoun, B. H., “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
2016
A. D. Kamakshi, Shrivastava, A., and Calhoun, B. H., “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
A. Roy, Grossmann, P., Vitale, S., and Calhoun, B., “A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
A. Shrivastava, Akella, D., and Calhoun, B. H., “A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, 2016.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
D. Akella, Shrivastava, A., Duan, C., and Calhoun, B. H., “A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 6, 2016.
H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H., “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in European Solid State Circuits Conference (ESSCIRC), 2016.

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