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A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic
A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic
H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H.,
“A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in
European Solid State Circuits Conference (ESSCIRC), 2016.
