VLSI Design Group

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Publications

2009
M. A. Hanson, Jr, H. C. Powell, Barth, A. T., Ringgenberg, K., Calhoun, B. H., Aylor, J. H., and Lach, J., Body Area Sensor Networks: Challenges and Opportunities, Computer, vol. 42, pp. 58–65, 2009.
A. D. Jurik, Bolus, J., Weaver, A. F., Calhoun, B. H., and Blalock., T. N., Mobile Health Monitoring Through Biotelemetry, in Bodynets, 2009.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., MSN: Memory Sensor for NBTI, in Techcon, 2009.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Design Time – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Standby – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
M. Putic, Di, L., Calhoun, B. H., and Lach, andJohn, Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
S. Khanna and Calhoun, B. H., Serial Sub-threshold Circuits for Ultra-Low-Power Systems, in International Symposium on Low Power Electronics and Design, 2009.
M. Bhargava, Nalam, S., Calhoun, B. H., and Mai, K., An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization, in TECHCON, 2009.
B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., Sub-threshold Circuit Design with Shrinking CMOS Devices, in International Symposium on Circuits and Systems, 2009.
B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors, in International Symposium on Circuits and Systems, 2009.
S. Nalam, Bhargava, M., Ringgenberg, K., Mai, K., and Calhoun, B. H., A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes, in ICCD, 2009, pp. 523-528.
2008
J. Wang, Nalam, S., and Calhoun, B. H., Analyzing Static and Dynamic Write Margin for Nanometer SRAMs, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
J. Wang and Calhoun, B. H., An Enhanced Adaptive Canary System for SRAM Standby Power Reduction, in TECHCON, 2008.
J. F. Ryan and Calhoun, B. H., Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation, in International Symposium on Quality Electronic Design, 2008, pp. 127-132.
L. Di, Putic, M., Lach, J., and Calhoun, B. H., Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling, in International Conference on Computer Design, pages 605-611, 2008.
A. Singhee, Wang, J., Calhoun, B. H., and Rutenbar, R. A., Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design, in International Conference on VLSI Design, India, 2008, pp. 131-136.
J. Wang and Calhoun, B. H., Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.
2006
B. H. Calhoun and Chandrakasan, A., A 256kb Sub-threshold SRAM in 65nm CMOS, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., Low Energy Digital Circuit Design, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.

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