Publications
] , “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms”, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
, “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs”, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “A 2.6-μW Sub-threshold Mixed-signal ECG SoC”, in Symposium on VLSI Circuits, 2009.
, “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.
, “Body Area Sensor Networks: Challenges and Opportunities”, Computer, vol. 42, pp. 58–65, 2009.
, “Mobile Health Monitoring Through Biotelemetry”, in Bodynets, 2009.
, “MSN: Memory Sensor for NBTI”, in Techcon, 2009.
, “Optimizing Power @ Design Time – Memory”, in Low Power Design Essentials, 2009.
, “Optimizing Power @ Standby – Memory”, in Low Power Design Essentials, 2009.
, “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design”, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
, “Serial Sub-threshold Circuits for Ultra-Low-Power Systems”, in International Symposium on Low Power Electronics and Design, 2009.
, “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization”, in TECHCON, 2009.
, “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
, “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
, “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction”, in TECHCON, 2008.
, “Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation”, in International Symposium on Quality Electronic Design, 2008, pp. 127-132.
, “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling”, in International Conference on Computer Design, pages 605-611, 2008.
, “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design”, in International Conference on VLSI Design, India, 2008, pp. 131-136.
, “Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.
, “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
, “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.