Publications
] , โA Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packetsโ, IEEE Journal of Solid-State Circuits, 2021.
, โDynamic Read VMIN and Yield Estimation for Nanoscale SRAMsโ, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB), โDynamic Write VMIN and Yield Estimation for Nanoscale SRAMsโ, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)
Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB), โGraph Coloring using Coupled Oscillator-based Dynamical Systemsโ, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
, โAn Integrated 2.4GHz -91.5dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2ฮผW at 100ms Latencyโ, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA (*Equally-Credited Authors), 2021.
, โMemGen: An Open-Source Framework for Autonomous Generation of Memory Macrosโ, in IEEE Custom Integrated Circuits Conference (CICC), 2021. kamineni2021.pdf (9.26 MB)
kamineni2021.pdf (9.26 MB), โModeling Energy-Aware Photoplethysmography Hardware for Personalized Health Care Applications Across Skin Phototypesโ, in IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021.
, โStacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Designโ, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
, โA 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/ยฐC Stability Using a Duty-Cycled Digital Frequency-Locked Loopโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB), โA -108dBm Sensitivity, -28dB SIR, 130nW to 41ฮผW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiverโ, in IEEE Custom Integrated Circuits Conference (CICC), 2020.
, โA 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodesโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)
A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB), โA 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoringโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, โAn 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reductionโ, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
, โAn 88.6nW Ozone Pollutant Sensing Interface IC with a 159 dB Dynamic Rangeโ, in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020.
, โApplication-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systemsโ, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
, โA comprehensive analysis of Auger generation impacted planar Tunnel FETsโ, Solid-State Electronics, 2020.
, โA Crystal-Less BLE Transmitter with -86dBm Frequency-Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packetโ, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, โFully Autonomous Mixed Signal SoC Design & Layout Generation Platformโ, IEEE Hot Chips 32 Symposium (HCS). 2020.
, โMinimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETsโ, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020. Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB), โA Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiverโ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, โAn Open-source Framework for Autonomous SoC Design with Analog Block Generationโ, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, โA Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Rangeโ, IEEE Solid-State Circuits Letters (SSCL), 2020. A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB), โSub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementationsโ, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper), 2020.
, โA Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Bandโ, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, โUsing synchronized oscillators to compute the maximum independent setโ, Nature Communications, 2020.