Robust Low Power VLSI

VLSI Design Group

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Journal Article

A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., “A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2021.

N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time”, IEEE Journal of Solid-State Circuits (JSSC), 2019.

B. H. Calhoun and Chandrakasan, A., “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.

K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.

S. Nalam and Calhoun, B. H., “5T SRAM with Asymmetric Sizing for Improved Read Stability”, JSSC, 2011.

D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., “A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic”, IEEE Solid-State Circuits Letters (SSCL), 2019.

A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)

Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.

B. H. Calhoun, Lach, J., Stankovic, J., Wentzloff, D. D., Whitehouse, K., Barth, A., Brown, J. K., Li, Q., Oh, S., Roberts, N., and Zhang, Y., “Body Sensor Networks: A Holistic Approach From Silicon to Users”, IEEE Proceedings, 2011.

B. H. Calhoun and Brooks, D., “Can Subthreshold and Near-Threshold Circuits Go Mainstream?”, IEEE Micro, vol. 30, pp. 80-85, 2010.

S. Z. Ahmed, Truesdell, D. S., Tan, Y., Calhoun, B. H., and Ghosh, A. W., “A comprehensive analysis of Auger generation impacted planar Tunnel FETs”, Solid-State Electronics, 2020.

X. Chen, Alghaihab, A., Shi, Y., Truesdell, D. S., Calhoun, B. H., and Wentzloff, D. D., “A Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packets”, IEEE Journal of Solid-State Circuits, 2021.

A. Shrivastava and Calhoun, B. H., “A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications”, 2013.

E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.

B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.

P. Beshay, Ryan, J. F., and Calhoun, B. H., “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers”, Journal of Low Power Electronics and Applications, 2013.

B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.

X. Liu, Agrawal, A., Tanaka, A., and Calhoun, B. H., “Distributed Energy Harvesting and Power Management Units for Self-Powered In-Fabric Sensing Networks”, 2024 IEEE Midwest Symposium on Circuits and Systems (MWSCAS), invited paper, 2024.

S. Gupta and Calhoun, B. H., “Dynamic Read V_MIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.

Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)

S. Gupta and Calhoun, B. H., “Dynamic Write V_MIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.

Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)

C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.

Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., “Energy Efficient Design for Body Sensor Nodes”, Journal of Low Power Electronics and Applications, 2011.

S. N. Wooters, Calhoun, B. H., and Blalock, T. N., “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.

J. Wang, Hoefler, A., and Calhoun, B. H., “An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction”, Transactions on VLSI Systems (TVLSI), 2011.

B. H. Calhoun, Ryan, J., Khanna, S., Putic, M., and Lach, J., “Flexible Circuits and Architectures for Ultra Low Power”, Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.

J. Moody, Dissanayake, A., Bishop, H. L., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.

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