Publications
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, “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
, “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
, “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, “A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, 2016.
, “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
, “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
, “A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 6, 2016.
, “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in European Solid State Circuits Conference (ESSCIRC), 2016.
, “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
, “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.
, “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.
, “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
, “Exploring Circuit Robustness to Power Supply Variation in Low-Voltage Latch and Register-Based Digital Systems”, in IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.
, “Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.”, in International Conference on VLSI Design, Kolkata, India, 2016.
, “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
, “Optimizing SRAM Bitcell Reliability and Energy for IoT Applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, “A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
, “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
, “A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems”, in International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.
, “A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting with 220mV Cold-Start and -14.5dBm, 915MHz RF Kick-Start”, IEEE Journal of Solid-State Circuits (JSSC), vol. 50, pp. 1820-1832, 2015.
, “A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations”, in Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015.
, “A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.