Robust Low Power VLSI
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2017
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., “Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems”, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
H. N. Patel, Mann, R. W., and Calhoun, B. H., “Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications”, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
H. N. Patel, Yahya, F. B., and Calhoun, B. H., “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
H. Qi, Ayorinde, O., and Calhoun, B. H., “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
2016
A. D. Kamakshi, Shrivastava, A., and Calhoun, B. H., “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
A. Roy, Grossmann, P., Vitale, S., and Calhoun, B., “A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
A. Shrivastava, Akella, D., and Calhoun, B. H., “A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, 2016.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
D. Akella, Shrivastava, A., Duan, C., and Calhoun, B. H., “A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 6, 2016.
H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H., “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in European Solid State Circuits Conference (ESSCIRC), 2016.
Y. Huang, Shrivastava, A., Barnes, L., and Calhoun, B. H., “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
N. Liu and Calhoun, B. H., “Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
W. Eberhardt, Wakefield, B., Casey, C., Murphy, C., Calhoun, B. H., and Reichmuth, C., “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.
W. Eberhardt, Wakefield, B., Casey, C., Murphy, C., Calhoun, B. H., and Reichmuth, C., “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.
H. Qi, Ayorinde, O., and Calhoun, B. H., “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
A. Roy and Calhoun, B., “Exploring Circuit Robustness to Power Supply Variation in Low-Voltage Latch and Register-Based Digital Systems”, in IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.
H. Patel, Yahya, F., and Calhoun, B. H., “Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.”, in International Conference on VLSI Design, Kolkata, India, 2016.
D. Kamakshi, Fojtik, M., Khailany, B., Kudva, S., Zhou, Y., and Calhoun, B. H., “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
H. Patel, Yahya, F., and Calhoun, B., “Optimizing SRAM Bitcell Reliability and Energy for IoT Applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.

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