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Author [ Title(Desc)] Type Year
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A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver, IEEE Journal of Solid-State Circuits, 2021.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., Chen, X., Wentzloff, D. D., and Calhoun, B. H., A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time, IEEE Journal of Solid-State Circuits (JSSC), 2019.
B. H. Calhoun and Chandrakasan, A., A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
A. Banerjee, Liu, N., Patel, H. N., and Calhoun, B. H., A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors, in 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, 2017.
B. H. Calhoun and Chandrakasan, A., A 256kb Sub-threshold SRAM in 65nm CMOS, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
S. Jocke, Bolus, J., Wooters, S. N., Jurik, A. D., Weaver, A. F., Blalock, T. N., and Calhoun, B. H., A 2.6-μW Sub-threshold Mixed-signal ECG SoC, in Symposium on VLSI Circuits, 2009.
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K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance, Journal of Solid State Circuits, 2014.
S. Li, Liu, X., and Calhoun, B. H., A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy Harvesting and Power Management Platform with 1.2×10^5 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up, in IEEE International Solid-State Circuits Conference (ISSCC), 2022.
A. Shrivastava, Craig, K., Roberts, N., Wentzloff, D. D., and Calhoun, B. H., A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems, in EEE International Solid-State Circuits Conference (ISSCC), 2015.
X. Liu, Truesdell, D. S., Faruqe, O., Parameswaran, L., Rickley, M., Kopanski, A., Cantley, L., Coon, A., Bernasconi, M., Wang, T., and Calhoun, B. H., A 33nW Fully Autonomous SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for mm-scale System-in-Fiber, in IEEE Transactions on Biomedical Circuits and Systems, Invited paper, 2023.PDF icon A_33nW_Fully_Autonomous_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_mm-scale_System-in-Fiber.pdf (16.09 MB)
D. Duvvuri, Shen, X., Bassirian, P., Bishop, H. L., Liu, X., Chen, C. - H., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., A 366 nW, -74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, 2021.
D. Akella, Shrivastava, A., Duan, C., and Calhoun, B. H., A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications, Journal of Low Power Electronics and Applications (JLPEA), vol. 6, 2016.
J. .Bolus, Calhoun, B. H., and .Blalock, T., 39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 16, 2014.
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D. S. Truesdell and Calhoun, B. H., A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019.PDF icon A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
A. Klinefelter, Roberts, N., Shakhsheer, Y., Gonzalez, P., Shrivastava, A., Roy, A., Craig, K., Faisal, M., Boley, J., Oh, S., Zhang, Y., Akella, D., Wentzloff, D. D., and Calhoun, B., A 6.45 μW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios, in ISSCC, San Francisco, CA, 2015.
A. Roy, Klinefelter, A., Yahya, F., Chen, X., Gonzalez, P., Lukas, C. J., Akella, D., Boley, J., Craig, K., Faisal, M., Oh, S., Roberts, N., Shakhsheer, Y., Shrivastava, A., Vasudevan, D., Wentzloff, D. D., and Calhoun, B., A 6.45μW Self-Powered SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems, IEEE Transactions on Biomedical Circuits and Systems, vol. 9, pp. 862-874, 2015.
S. Gupta, Truesdell, D. S., and Calhoun, B. H., A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.PDF icon A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)
D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)

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