B. H. Calhoun and Chandrakasan, A., “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.Calhoun_JSSC07.pdfCalhoun_ISCAS2009_wear_paper.pdf Google ScholarBibTexRTFTaggedMARCXMLRIS