Publications
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, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
, “REESES: Rapid Efficient Energy Scalable ElectronicS”, in GOMAC Tech, 2010.
, “A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber”, in IEEE International Solid-State Circuits Conference (ISSCC), 2023.
15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB)
15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB), “Serial Sub-threshold Circuits for Ultra-Low-Power Systems”, in International Symposium on Low Power Electronics and Design, 2009.
, “Stepped Supply Voltage Switching for Energy Constrained Systems”, in ISQED, 2011.
, “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
, “A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic”, in GOMAC Tech, 2011.
, “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.
, “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms”, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
, “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
, “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
, “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics”, in Proc. of GOMAC Tech, 2007.
, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
, “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis”, Journal of Low Power Electronics and Applications (JLPEA), 2018.
, “A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications”, IEEE Transactions on Biomedical Circuits and Systems, 2019. 08625544.pdf (3.22 MB)
08625544.pdf (3.22 MB), “A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications”, IEEE Transactions on Biomedical Circuits and Systems, 2019. 08625544.pdf (3.22 MB)
08625544.pdf (3.22 MB), “A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting with 220mV Cold-Start and -14.5dBm, 915MHz RF Kick-Start”, IEEE Journal of Solid-State Circuits (JSSC), vol. 50, pp. 1820-1832, 2015.
, “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time”, IEEE Journal of Solid-State Circuits (JSSC), 2019.
, “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.
, “A 6.45μW Self-Powered SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems”, IEEE Transactions on Biomedical Circuits and Systems, vol. 9, pp. 862-874, 2015.
, “A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic”, IEEE Solid-State Circuits Letters (SSCL), 2019. A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)