Publications
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“A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range”, IEEE Solid-State Circuits Letters (SSCL), 2020. A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
, Sub-threshold Design for Ultra Low-Power Systems. Springer, 2006.
, “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array”, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
, “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs”, in Solid State Circuits Technologies, INTECH, 2010.
, “A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm”. 2011 Workshop on RFID Security, 2011.
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