TY - JOUR T1 - A Sub-µW Energy-Performance-Aware IoT SoC with a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization JF - IEEE Journal of Solid-State Circuits Y1 - 2024 A1 - Xinjian Liu A1 - Sumanth Kamineni A1 - Jacob Breiholz A1 - Benton H. Calhoun A1 - Shuo Li ER - TY - CONF T1 - Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems Y1 - 2023 A1 - Shourya Gupta A1 - Shuo Li A1 - Benton H. Calhoun JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems ER - TY - CONF T1 - A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber T2 - IEEE International Solid-State Circuits Conference (ISSCC) Y1 - 2023 A1 - Xinjian Liu A1 - Daniel S. Truesdell A1 - Omar Faruqe A1 - Lalitha Parameswaran A1 - Michael Rickley A1 - Andrew Kopanski A1 - Lauren Cantley A1 - Austin Coon A1 - Matthew Bernasconi A1 - Tairan Wang A1 - Benton H. Calhoun JF - IEEE International Solid-State Circuits Conference (ISSCC) ER - TY - JOUR T1 - A Sub-nW 93% Peak Efficiency Buck Converter with Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control JF - IEEE Journal of Solid-State Circuits, (invited paper) Y1 - 2022 A1 - Xinjian Liu A1 - Benton H. Calhoun A1 - Shuo Li ER - TY - CONF T1 - Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design T2 - 2021 IEEE International Symposium on Circuits and Systems (ISCAS) Y1 - 2021 A1 - Anjana Dissanayake A1 - Steven M. Bowers A1 - Benton H. Calhoun JF - 2021 IEEE International Symposium on Circuits and Systems (ISCAS) ER - TY - JOUR T1 - A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range JF - IEEE Solid-State Circuits Letters (SSCL) Y1 - 2020 A1 - Daniel S. Truesdell A1 - Benton H. Calhoun ER - TY - CONF T1 - Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations T2 - 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper) Y1 - 2020 A1 - Shuo Li A1 - Benton H. Calhoun JF - 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper) ER - TY - CONF T1 - Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications T2 - 23rd IEEE International Symposium on On-Line Testing and Robust System Design Y1 - 2017 A1 - Harsh N. Patel A1 - Randy W. Mann A1 - Benton H. Calhoun JF - 23rd IEEE International Symposium on On-Line Testing and Robust System Design PB - IEEE CY - Thessaloniki, Greece U1 - IOLTS_2017_Poster_Paper_Submitted.pdf|IOLTS_2017_Poster_Paper_Submitted.pdf ER - TY - CONF T1 - Subthreshold SRAM: Challenges, Design Decisions, and Solutions T2 - 60th IEEE International Midwest Symposium on Circuits and Systems Y1 - 2017 A1 - Harsh N. Patel A1 - Farah B. Yahya A1 - Benton H. Calhoun JF - 60th IEEE International Midwest Symposium on Circuits and Systems PB - IEEE CY - Boston, MA, USA U1 - MWCAS_2017_Final_IEEE_Submitted.pdf|MWCAS_2017_Final_IEEE_Submitted.pdf ER - TY - JOUR T1 - A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs JF - J. Low Power Electron. Appl. (JLPEA) Y1 - 2016 A1 - F. Yahya A1 - H. Patel A1 - Boley, J. A1 - A. Banerjee A1 - B. H. Calhoun VL - 6 U1 - A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf|A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf ER - TY - CONF T1 - Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset T2 - International Symposium on Quality Electronic Design Y1 - 2015 A1 - Boley, J. A1 - B. H. Calhoun JF - International Symposium on Quality Electronic Design ER - TY - CONF T1 - Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM T2 - Design Automation Conference (DAC) Y1 - 2014 A1 - P. Beshay A1 - V. Chandra A1 - R. Aitken A1 - B. H. Calhoun JF - Design Automation Conference (DAC) ER - TY - CONF T1 - SRAM Sense Amplifier Offset Cancellation Using BTI Stress T2 - Subthreshold Microelectronics Conference Y1 - 2012 A1 - Peter Beshay A1 - Jonathan Bolus A1 - Travis Blalock A1 - Vikas Chandra A1 - Benton H. Calhoun JF - Subthreshold Microelectronics Conference U1 - Beshay_BTI_subVT12_poster.pdf|Beshay_BTI_subVT12_poster.pdf ER - TY - CONF T1 - Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry T2 - Subthreshold Microelectronics Conference Y1 - 2012 A1 - Peter Beshay A1 - Joseph F. Ryan A1 - Benton H. Calhoun JF - Subthreshold Microelectronics Conference U1 - Beshay_DAZ_subVT12_paper.pdf|Beshay_DAZ_subVT12_paper.pdf ER - TY - CONF T1 - Stepped Supply Voltage Switching for Energy Constrained Systems T2 - ISQED Y1 - 2011 A1 - Sudhanshu Khanna A1 - Kyle Craig A1 - Yousef Shakhsheer A1 - Saad Arrabi A1 - John Lach A1 - Benton Calhoun JF - ISQED U1 - Khanna_ISQED2011_paper.pdf|Khanna_ISQED2011_paper.pdf ER - TY - ABST T1 - A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm Y1 - 2011 A1 - Y. Yu A1 - J. Huang A1 - S. Khanna A1 - B. H. Calhoun A1 - J. Lach A1 - A. Shelat A1 - D. Evans CY - 2011 Workshop on RFID Security ER - TY - ABST T1 - A sub-threshold clock and data recovery circuit for a wireless sensor node Y1 - 2011 A1 - Aatmesh Shrivastava A1 - Benton H. Calhoun ER - TY - CONF T1 - A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic T2 - GOMAC Tech Y1 - 2011 A1 - Benton H. Calhoun A1 - Yanqing Zhang A1 - Sudhanshu Khanna A1 - Kyle Craig A1 - Yousef Shakhsheer A1 - John Lach JF - GOMAC Tech ER - TY - CONF T1 - SRAM-Based NBTI/PBTI Sensor System Design T2 - Design Automation Conference (DAC) Y1 - 2010 A1 - Jerry Qi A1 - Jiajing Wang A1 - Benton H. Calhoun A1 - Mircea Stan JF - Design Automation Conference (DAC) CY - San Diego, CA U1 - Qi_DAC2010_paper.pdf|Qi_DAC2010_paper.pdf ER - TY - CHAP T1 - Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs T2 - Solid State Circuits Technologies Y1 - 2010 A1 - Jiajing Wang A1 - Benton H. Calhoun ED - Jacobus W. Swart JF - Solid State Circuits Technologies PB - INTECH SN - 978-953-307-045-2 UR - http://sciyo.com/articles/show/title/standby-supply-voltage-minimization-for-reliable-nanoscale-srams U1 - standby_supply_voltage_minimization_for_reliable_nanoscale_srams.pdf|standby_supply_voltage_minimization_for_reliable_nanoscale_srams.pdf ER - TY - CONF T1 - A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS T2 - Custom Integrated Circuits Conference (CICC) Y1 - 2010 A1 - Joseph F. Ryan A1 - Benton H. Calhoun JF - Custom Integrated Circuits Conference (CICC) U1 - Ryan_CICC2010.pdf|Ryan_CICC2010.pdf ER - TY - CONF T1 - System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms T2 - International Symposium on Circuits and Systems (ISCAS) Y1 - 2010 A1 - Benton H. Calhoun A1 - Sudhanshu Khanna A1 - Yanqing Zhang A1 - Joseph Ryan A1 - Brian Otis JF - International Symposium on Circuits and Systems (ISCAS) CY - Paris, France UR - http://class6.ee.virginia.edu/bentemp/drupal/files/Calhoun_ISCAS2010.pdf U1 - Calhoun_ISCAS2010.pdf|Calhoun_ISCAS2010.pdf ER - TY - CONF T1 - Serial Sub-threshold Circuits for Ultra-Low-Power Systems T2 - International Symposium on Low Power Electronics and Design Y1 - 2009 A1 - Sudhanshu Khanna A1 - Benton H. Calhoun JF - International Symposium on Low Power Electronics and Design U1 - Khanna_ISLPED09_paper.pdf|Khanna_ISLPED09_paper.pdf ER - TY - CONF T1 - An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization T2 - TECHCON Y1 - 2009 A1 - M. Bhargava A1 - S. Nalam A1 - B. H. Calhoun A1 - K. Mai AB - SRAM design in scaled technologies increasingly requires circuit innovations such as read/write assist techniques or alternative bitcells to ensure even basic functionality. However, the lack of a quick mechanism for understanding the impact of these circuit level changes on system level metrics makes accurate assessments of new circuit techniques difficult. Thus, we introduce Virtual Prototyper (ViPro), a tool that helps circuit designers explore this large design space by rapidly generating optimized virtual prototypes of complete SRAM macros. ViPro does this by allowing SRAM component specification with varying levels of detail – from ‘black-box’ descriptions to complete netlists – and by incorporating those components into a hierarchical model that captures circuit and architectural features of the SRAM to optimize a complete prototype. SRAM designers can use ViPro to generate base-case prototypes, which provide starting points for design space exploration, or to assess the impact of a low level circuit innovation on the overall SRAM design. JF - TECHCON U1 - Bhargava_TECHCON09_paper.pdf|Bhargava_TECHCON09_paper.pdf ER - TY - CONF T1 - Sub-threshold Circuit Design with Shrinking CMOS Devices T2 - International Symposium on Circuits and Systems Y1 - 2009 A1 - B. H. Calhoun A1 - S. Khanna A1 - Mann, R. A1 - J. Wang JF - International Symposium on Circuits and Systems U1 - Calhoun_ISCAS2009subvt_slides.pdf|Calhoun_ISCAS2009subvt_slides.pdf ER - TY - CONF T1 - Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors T2 - International Symposium on Circuits and Systems Y1 - 2009 A1 - Benton H. Calhoun A1 - Jonathan Bolus A1 - Sudhanshu Khanna A1 - Andrew D. Jurik A1 - Alf F. Weaver A1 - Travis N. Blalock JF - International Symposium on Circuits and Systems U1 - Calhoun_ISCAS2009_wear_slides.pdf|Calhoun_ISCAS2009_wear_slides.pdf ER - TY - CONF T1 - Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array T2 - European Solid State Circuits Conference (ESSCIRC) Y1 - 2007 A1 - Jiajing Wang A1 - Amith Singhee A1 - Rob A. Rutenbar A1 - Benton H. Calhoun JF - European Solid State Circuits Conference (ESSCIRC) U1 - Wang_ESSCIRC07_paper.pdf|Wang_ESSCIRC07_paper.pdf ER - TY - JOUR T1 - Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS JF - IEEE Journal of Solid-State Circuits (JSSC) Y1 - 2006 A1 - Benton H. Calhoun A1 - Anantha Chandrakasan VL - 41 U1 - Calhoun_JSSC06_snm.pdf|Calhoun_JSSC06_snm.pdf ER - TY - BOOK T1 - Sub-threshold Design for Ultra Low-Power Systems Y1 - 2006 A1 - Alice Wang A1 - Benton H. Calhoun, Anantha Chandrakasan PB - Springer ER - TY - CONF T1 - Sub-threshold Design: The Challenges of Minimizing Circuit Energy T2 - International Symposium on Low Power Electronics and Design (ISLPED) Y1 - 2006 A1 - Benton H. Calhoun A1 - Alice Wang A1 - Naveen Verma A1 - Anantha Chandrakasan JF - International Symposium on Low Power Electronics and Design (ISLPED) U1 - 2006_Calhoun_ISLPED.pdf|2006_Calhoun_ISLPED.pdf ER - TY - JOUR T1 - Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures JF - IEEE Journal of Solid-State Circuits (JSSC) Y1 - 2004 A1 - Benton H. Calhoun A1 - Anantha Chandrakasan VL - 39 U1 - jssc04_canary.pdf|jssc04_canary.pdf ER - TY - CONF T1 - Standby Voltage Scaling for Reduced Power T2 - Custom Integrated Circuits Conference (CICC) Y1 - 2003 A1 - Benton Calhoun A1 - Anantha Chandrakasan JF - Custom Integrated Circuits Conference (CICC) U1 - 2003_Calhoun_CICC.pdf|2003_Calhoun_CICC.pdf ER -