X.  Liu, Kamineni, S., Breiholz, J., Calhoun, B. H., and Li, S., ?A Sub-µW Energy-Performance-Aware IoT SoC with a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization?, IEEE Journal of Solid-State Circuits, 2024.

S.  Gupta, Li, S., and Calhoun, B. H., ?Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS?, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2023.

X.  Liu, Truesdell, D. S., Faruqe, O., Parameswaran, L., Rickley, M., Kopanski, A., Cantley, L., Coon, A., Bernasconi, M., Wang, T., and Calhoun, B. H., ?A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber?, in IEEE International Solid-State Circuits Conference (ISSCC), 2023.

X.  Liu, Calhoun, B. H., and Li, S., ?A Sub-nW 93% Peak Efficiency Buck Converter with Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control?, IEEE Journal of Solid-State Circuits, (invited paper), 2022.

A.  Dissanayake, Bowers, S. M., and Calhoun, B. H., ?Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design?, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.

D. S.  Truesdell and Calhoun, B. H., ?A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range?, IEEE Solid-State Circuits Letters (SSCL), 2020.

S.  Li and Calhoun, B. H., ?Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations?, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper), 2020.

H. N.  Patel, Mann, R. W., and Calhoun, B. H., ?Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications?, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.

H. N.  Patel, Yahya, F. B., and Calhoun, B. H., ?Subthreshold SRAM: Challenges, Design Decisions, and Solutions?, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.

F.  Yahya, Patel, H., Boley, J., Banerjee, A., and Calhoun, B. H., ?A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs?, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.

J.  Boley and Calhoun, B. H., ?Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset?, in International Symposium on Quality Electronic Design, 2015.

P.  Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., ?Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM?, in Design Automation Conference (DAC), 2014.

P.  Beshay, Bolus, J., Blalock, T., Chandra, V., and Calhoun, B. H., ?SRAM Sense Amplifier Offset Cancellation Using BTI Stress?, in Subthreshold Microelectronics Conference, 2012.

P.  Beshay, Ryan, J. F., and Calhoun, B. H., ?Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry?, in Subthreshold Microelectronics Conference, 2012.

S.  Khanna, Craig, K., Shakhsheer, Y., Arrabi, S., Lach, J., and Calhoun, B., ?Stepped Supply Voltage Switching for Energy Constrained Systems?, in ISQED, 2011.

Y.  Yu, Huang, J., Khanna, S., Calhoun, B. H., Lach, J., Shelat, A., and Evans, D., ?A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm?. 2011 Workshop on RFID Security, 2011.

A.  Shrivastava and Calhoun, B. H., ?A sub-threshold clock and data recovery circuit for a wireless sensor node?. 2011.

B. H.  Calhoun, Zhang, Y., Khanna, S., Craig, K., Shakhsheer, Y., and Lach, J., ?A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic?, in GOMAC Tech, 2011.

J.  Qi, Wang, J., Calhoun, B. H., and Stan, M., ?SRAM-Based NBTI/PBTI Sensor System Design?, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.

J.  Wang and Calhoun, B. H., ?Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs?, in Solid State Circuits Technologies, J. W.  Swart, Ed. INTECH, 2010.

J. F.  Ryan and Calhoun, B. H., ?A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS?, in Custom Integrated Circuits Conference (CICC), 2010.

B. H.  Calhoun, Khanna, S., Zhang, Y., Ryan, J., and Otis, B., ?System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms?, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.

S.  Khanna and Calhoun, B. H., ?Serial Sub-threshold Circuits for Ultra-Low-Power Systems?, in International Symposium on Low Power Electronics and Design, 2009.

M.  Bhargava, Nalam, S., Calhoun, B. H., and Mai, K., ?An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization?, in TECHCON, 2009.

B. H.  Calhoun, Khanna, S., Mann, R., and Wang, J., ?Sub-threshold Circuit Design with Shrinking CMOS Devices?, in International Symposium on Circuits and Systems, 2009.

B. H.  Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., ?Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors?, in International Symposium on Circuits and Systems, 2009.

J.  Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., ?Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array?, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.

B. H.  Calhoun and Chandrakasan, A., ?Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS?, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.

A.  Wang and Calhoun, A. Chandrakas, Sub-threshold Design for Ultra Low-Power Systems. Springer, 2006.

B. H.  Calhoun, Wang, A., Verma, N., and Chandrakasan, A., ?Sub-threshold Design: The Challenges of Minimizing Circuit Energy?, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.

B. H.  Calhoun and Chandrakasan, A., ?Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures?, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.

B.  Calhoun and Chandrakasan, A., ?Standby Voltage Scaling for Reduced Power?, in Custom Integrated Circuits Conference (CICC), 2003, pp. 639-642.