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R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.

J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.

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H. L. Bishop, Wang, P., Fan, D., Lach, J., and Calhoun, B. H., “Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems”, in Global Internet of Things Summit (GIoTS), 2018.

B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., “Low Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.

O. Abdelatty, Bishop, H., Shi, Y., Chen, X., Alghaihab, A., Calhoun, B., and Wentzloff, D., “A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Cracow, Poland, 2019.

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J. Wang and Calhoun, B. H., “Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations”, Transactions on VLSI Systems (TVLSI), 2011.

A. D. Jurik, Bolus, J., Weaver, A. F., Calhoun, B. H., and Blalock., T. N., “Mobile Health Monitoring Through Biotelemetry”, in Bodynets, 2009.

B. H. Calhoun, Wang, A., and Chandrakasan, A., “Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.

K. Flynn, Ownby, N., Wang, P., and Calhoun, B. H., “Modeling Energy-Aware Photoplethysmography Hardware for Personalized Health Care Applications Across Skin Phototypes”, in IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021.

J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “MSN: Memory Sensor for NBTI”, in Techcon, 2009.

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T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.

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A. Singhee, Wang, J., Calhoun, B. H., and Rutenbar, R. A., “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design”, in International Conference on VLSI Design, India, 2008, pp. 131-136.

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X. Liu, Truesdell, D. S., Faruqe, O., Parameswaran, L., Rickley, M., Kopanski, A., Cantley, L., Coon, A., Bernasconi, M., Wang, T., and Calhoun, B. H., “A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber”, in IEEE International Solid-State Circuits Conference (ISSCC), 2023.

15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB)

J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “SRAM-Based NBTI/PBTI Sensor System Design”, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.

J. Wang and Calhoun, B. H., “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs”, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.

J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array”, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.

B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.

A. Wang and Calhoun, A. Chandrakas, Sub-threshold Design for Ultra Low-Power Systems. Springer, 2006.

B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., “Sub-threshold Design: The Challenges of Minimizing Circuit Energy”, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.

B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.

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J. Wang and Calhoun, B. H., “Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.

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