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L

J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.

I

J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.

R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.

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S. Arrabi, Moore, D., Wang, L., Skadron, K., and Calhoun, B. H., “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems”, in International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.

Y. Zhang and Calhoun, B. H., “Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits”, in International Symposium on Quality Electronic Design (ISQED), 2014.

E

A. Klinefelter, Ryan, J., Tschanz, J., and Calhoun, B. H., “Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications”, in International Symposium on Circuits and Systems (ISCAS), 2015.

D

S. Nalam, Chandra, V., Aitken, R. C., and Calhoun, B. H., “Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM”, in Design Automation and Test Europe (DATE), 2011.

W. Eberhardt, Wakefield, B., Casey, C., Murphy, C., Calhoun, B. H., and Reichmuth, C., “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.

N. Liu and Calhoun, B. H., “Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.

Y. Huang, Shrivastava, A., Barnes, L., and Calhoun, B. H., “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.

C

Y. Shakhsheer, Zhang, Y., Otis, B., and Calhoun, B. H., “A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS”, Custom Integrated Circuits Conference. San Jose, 2012.

B. H. Meyer, Calhoun, B. H., Lach, J. C., and Skadron, K., “Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy”, CASES. 2011.

J. B. Stocking, Eberhardt, W. C., Shakhsheer, Y. A., Paulus, J. R., Appleby, M., and Calhoun, B. H., “A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing”, in IEEE Sensors, 2010.

B

M. A. Hanson, Jr, H. C. Powell, Barth, A. T., Ringgenberg, K., Calhoun, B. H., Aylor, J. H., and Lach, J., “Body Area Sensor Networks: Challenges and Opportunities”, Computer, vol. 42, pp. 58–65, 2009.

W. C. Eberhardt, Shakhsheer, Y. A., and Calhoun, B. H., “A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability”, in IEEE Sensors, Limrick, Ireland, 2011.

A

S. Nalam and Calhoun, B. H., “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.

S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN”, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.

J. Boley, Calhoun, B. H., and Wang, J., “Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”. 2011.

J. Wang, Nalam, S., and Calhoun, B. H., “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.

J. F. Ryan, Khanna, S., and Calhoun, B. H., “An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal”, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.

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Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., “A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V”, in Custom Integrated Circuits Conference, San Jose, 2011.

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H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H., “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in European Solid State Circuits Conference (ESSCIRC), 2016.

3

J. .Bolus, Calhoun, B. H., and .Blalock, T., “39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 16, 2014.

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