%0 Conference Paper %B 2017 IEEE Custom Integrated Circuits Conference (CICC) %D 2017 %T A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors %A A. Banerjee %A N. Liu %A H. N. Patel %A B. H. Calhoun %E J. Poulton %E C. T. Gray %B 2017 IEEE Custom Integrated Circuits Conference (CICC) %C Austin, TX, 2017 %G eng %1 CICC2017_SRAM.pdf|Banerjee_CICC2017.pdf %0 Journal Article %J J. Low Power Electron. Appl. (JLPEA) %D 2016 %T A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications %A D. Akella Kamakshi %A A. Shrivastava %A B. H. Calhoun %B J. Low Power Electron. Appl. (JLPEA) %V 6 %G eng %1 A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications.pdf|A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications.pdf %0 Journal Article %J IEEE Journal of Solid-State Circuits (JSSC) %D 2016 %T A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply %A A. Shrivastava %A Akella, D. %A B. H. Calhoun %B IEEE Journal of Solid-State Circuits (JSSC) %V 51 %G eng %1 A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply.pdf|A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply.pdf %0 Conference Paper %B IEEE International Solid-State Circuits Conference (ISSCC) %D 2016 %T A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS %A Roberts, N. E. %A K. Craig %A A. Shrivastava %A S. N. Wooters %A Y. Shakhsheer %A B. H. Calhoun %A Wentzloff, D. D. %B IEEE International Solid-State Circuits Conference (ISSCC) %G eng %1 A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS.pdf|A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS.pdf %0 Journal Article %J Journal of Low Power Electronics and Applications (JLPEA) %D 2016 %T A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications %A Akella, D. %A A. Shrivastava %A C. Duan %A B. H. Calhoun %B Journal of Low Power Electronics and Applications (JLPEA) %V 6 %G eng %1 A 36nW, 7 ppmoC Fully On-Chip Clock Source System for Ultra-Low Power Applications.pdf|A 36nW, 7 ppmoC Fully On-Chip Clock Source System for Ultra-Low Power Applications.pdf %0 Conference Paper %B European Solid State Circuits Conference (ESSCIRC) %D 2016 %T A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic %A H. N. Patel %A Roy, A. %A F. B. Yahya %A N. Liu %A K. Kumeno %A M. Yasuda %A A. Harada %A T. Ema %A B. H. Calhoun %B European Solid State Circuits Conference (ESSCIRC) %G eng %1 A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf|A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf %0 Journal Article %J J. Low Power Electron. Appl. (JLPEA) %D 2016 %T A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs %A Y. Huang %A A. Shrivastava %A L. Barnes %A B. H. Calhoun %B J. Low Power Electron. Appl. (JLPEA) %V 6 %G eng %1 A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs.pdf|A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs.pdf %0 Conference Paper %B IEEE Computer Society Annual Symposium on VLSI (ISVLSI) %D 2016 %T Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool %A N. Liu %A B. H. Calhoun %B IEEE Computer Society Annual Symposium on VLSI (ISVLSI) %G eng %1 ISVLSI-2016_Poster_ViPro.pdf|ISVLSI-2016_Poster_ViPro.pdf %0 Journal Article %J Bioinspiration and Biomimetics %D 2016 %T Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array %A W. Eberhardt %A B. Wakefield %A C. Casey %A C. Murphy %A B. H. Calhoun %A C. Reichmuth %B Bioinspiration and Biomimetics %G eng %1 Development of an artificial sensor for hydrodynamic detection inspired by a seal\textquoterights whisker array.pdf| %0 Conference Paper %B ASYNC %D 2016 %T Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks %A D. Kamakshi %A M. Fojtik %A B. Khailany %A S. Kudva %A Y. Zhou %A B. H. Calhoun %B ASYNC %G eng %1 Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks.pdf|Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks.pdf %0 Journal Article %J J. Low Power Electron. Appl. (JLPEA) %D 2016 %T A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs %A F. Yahya %A H. Patel %A Boley, J. %A A. Banerjee %A B. H. Calhoun %B J. Low Power Electron. Appl. (JLPEA) %V 6 %G eng %1 A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf|A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf %0 Conference Paper %B IEDM %D 2016 %T A Tunnel FET Design for High-Current, 120 mV Operation %A P. Long %A J. Z. Huang %A M. Povolotskyi %A D. Verreck %A J. Charles %A T. Kubis %A G. Klimeck %A M. J.W. Rodwell %A B. H. Calhoun %B IEDM %G eng %0 Journal Article %J IEEE Journal of Solid-State Circuits (JSSC) %D 2015 %T A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting with 220mV Cold-Start and -14.5dBm, 915MHz RF Kick-Start %A A. Shrivastava %A Roberts, N. E. %A O. U. Khan %A Wentzloff, D. D. %A B. H. Calhoun %B IEEE Journal of Solid-State Circuits (JSSC) %V 50 %P 1820-1832 %8 08/2015 %G eng %0 Conference Paper %B IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) %D 2015 %T A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs %A Y. Huang %A A. Shrivastava %A B. H. Calhoun %B IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) %G eng %0 Conference Paper %B EEE International Solid-State Circuits Conference (ISSCC) %D 2015 %T A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems %A A. Shrivastava %A K. Craig %A N. Roberts %A Wentzloff, D. D. %A B. H. Calhoun %B EEE International Solid-State Circuits Conference (ISSCC) %G eng %0 Conference Paper %B International Symposium on Circuits and Systems (ISCAS) %D 2015 %T Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications %A Klinefelter, A. %A J. Ryan %A Tschanz, J. %A B. H. Calhoun %B International Symposium on Circuits and Systems (ISCAS) %8 05/2015 %G eng %0 Conference Paper %B International Symposium on Quality Electronic Design %D 2015 %T Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset %A Boley, J. %A B. H. Calhoun %B International Symposium on Quality Electronic Design %8 03/2015 %G eng %0 Conference Paper %B GOMACTech %D 2015 %T Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors %A Y. Shakhsheer %A A. Shrivastava %A N. Roberts %A K. Craig %A S. Wooters %A Wentzloff, D. D. %A B. H. Calhoun %B GOMACTech %G eng %0 Conference Paper %B HOT Chips %D 2015 %T Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT %A B. H. Calhoun %A Wentzloff, D. D. %B HOT Chips %G eng %0 Conference Paper %B IEEE Custom Integrated Circuits Conference (CICC) %D 2014 %T A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting %A A. Shrivastava %A D. Wentzloff %A B. H. Calhoun %B IEEE Custom Integrated Circuits Conference (CICC) %8 2014 %G eng %1 2014_Aatmesh_CICC.pdf|2014_Aatmesh_CICC.pdf %0 Conference Paper %B Symposium on VLSI Circuits %D 2014 %T A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages %A A. Shrivastava %A Y. K. Ramadass %A S. Khanna %A S. Bartling %A B. H. Calhoun %B Symposium on VLSI Circuits %8 2014 %G eng %1 06858364.pdf %0 Journal Article %J Journal of Low Power Electronics and Applications (JLPEA) %D 2014 %T 39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation %A J.Bolus %A B. H. Calhoun %A T.Blalock %B Journal of Low Power Electronics and Applications (JLPEA) %V 4 %P 16 %8 09/2014 %G eng %& 252 %0 Conference Paper %B International Symposium on Quality Electronic Design (ISQED) %D 2014 %T Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits %A Y. Zhang %A B. H. Calhoun %B International Symposium on Quality Electronic Design (ISQED) %8 02,2014 %G eng %0 Conference Paper %B International Symposium on Field-Programmable Custom Computing Machines (FCCM) %D 2014 %T Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems %A S. Arrabi %A D. Moore %A L. Wang %A K. Skadron %A B. H. Calhoun %B International Symposium on Field-Programmable Custom Computing Machines (FCCM) %8 2014 %G eng %1 06861633.pdf|06861633.pdf %0 Conference Paper %B GOMAC Tech %D 2014 %T LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications %A J. J. Granacki %A B. H. Calhoun %A A. R. Dasu %A M. Jagasivamani %A L. McIlrath %A M. Fritze %B GOMAC Tech %8 2014 %G eng %0 Conference Paper %B International Conference on IC Design and Technology (ICICDT) %D 2014 %T Modeling SRAM Dynamic VMIN %A Boley, J. %A V. Chandra %A R. Aitken %A B. H. Calhoun %B International Conference on IC Design and Technology (ICICDT) %8 06/2014 %G eng %0 Conference Paper %B VLSI Design Conference %D 2014 %T Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories %A S. Khanna %A S. V. Nalam %A B. H. Calhoun %B VLSI Design Conference %8 2014 %G eng %1 06733120.pdf|06733120.pdf %0 Conference Paper %B S3S Conference %D 2014 %T A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs %A Klinefelter, A. %A B. H. Calhoun %B S3S Conference %C Monterey, CA %8 10/2014 %G eng %1 s3s_final_klinefelter_0.pdf|s3s_final_klinefelter_0.pdf %0 Conference Paper %B International Symposium on Quality Electronic Design (ISQED) %D 2014 %T A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs %A A. Banerjee %A M. Sinangil %A J. Poulton %A C. T. Gray %A B. H. Calhoun %B International Symposium on Quality Electronic Design (ISQED) %8 02,2014 %G eng %1 06783299.pdf|06783299.pdf %0 Conference Paper %B Design Automation Conference (DAC) %D 2014 %T Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM %A P. Beshay %A V. Chandra %A R. Aitken %A B. H. Calhoun %B Design Automation Conference (DAC) %G eng %0 Journal Article %J Journal of Low Power Electronics and Applications (JLPEA) %D 2014 %T An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications %A A. Banerjee %A B. H. Calhoun %B Journal of Low Power Electronics and Applications (JLPEA) %V 4 %P 19 %8 05,2014 %G eng %& 119 %0 Journal Article %J Journal of Low Power Electronics and Applications %D 2012 %T Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin %A James Boley %A Jiajing Wang %A B. H. Calhoun %B Journal of Low Power Electronics and Applications %8 04/2012 %G eng %1 Boley_JLPEA2012.pdf|Boley_JLPEA2012.pdf %0 Journal Article %J Journal of Low Power Electronics and Applications (JLPEA) %D 2012 %T Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN %A Boley, J. %A J. Wang %A B. H. Calhoun %B Journal of Low Power Electronics and Applications (JLPEA) %V 2 %P 12 %8 04/2012 %G eng %1 Boley_JLPEA2012.pdf|Boley_JLPEA2012.pdf %& 143 %0 Conference Proceedings %B Custom Integrated Circuits Conference %D 2012 %T A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS %A Y. Shakhsheer %A Y. Zhang %A B. Otis %A B. H. Calhoun %B Custom Integrated Circuits Conference %C San Jose %8 09/2012 %G eng %1 Shakhsheer_CICC2012.pdf|Shakhsheer_CICC2012.pdf %0 Journal Article %J Transactions on VLSI Systems (TVLSI) %D 2012 %T Tracking On-Chip Age Using Distributed, Embedded Sensors %A S. N. Wooters %A A. C. Cabe %A Z. Qi %A J. Wang %A R. W. Mann %A B. H. Calhoun %A M. R. Stan %A T. N. Blalock %B Transactions on VLSI Systems (TVLSI) %V 20 %P 12 %8 11/2012 %G eng %& 1974 %0 Conference Paper %B Custom Integrated Circuits Conference %D 2011 %T A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V %A Y. Shakhsheer %A S. Khanna %A K. Craig %A S. Arrabi %A J. Lach %A B. H. Calhoun %B Custom Integrated Circuits Conference %C San Jose %8 09/2011 %G eng %1 PDVS_CICC2011_Final.pdf|PDVS_CICC2011_Final.pdf %0 Conference Paper %B Internation Symposium on Lower Power Electronics and Design (ISLPED) %D 2011 %T An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal %A J. F. Ryan %A S. Khanna %A B. H. Calhoun %B Internation Symposium on Lower Power Electronics and Design (ISLPED) %G eng %0 Generic %D 2011 %T Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin %A Boley, J. %A B. H. Calhoun %A J. Wang %G eng %0 Conference Paper %B IEEE Sensors %D 2011 %T A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability %A W.C. Eberhardt %A Y.A. Shakhsheer %A B. H. Calhoun %B IEEE Sensors %C Limrick, Ireland %8 10/2011 %G eng %1 Eberhardt_IEEESensors2011.pdf|Eberhardt_IEEESensors2011.pdf %0 Conference Proceedings %B CASES %D 2011 %T Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy %A B. H. Meyer %A B. H. Calhoun %A J. C. Lach %A K. Skadron %B CASES %G eng %0 Conference Paper %B Design Automation and Test Europe (DATE) %D 2011 %T Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM %A S. Nalam %A V. Chandra %A R. C. Aitken %A B. H. Calhoun %B Design Automation and Test Europe (DATE) %8 03/2011 %G eng %1 Nalam_DATE2011_paper.PDF|Nalam_DATE2011_paper.PDF %0 Journal Article %J Transactions on VLSI Systems (TVLSI) %D 2011 %T Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations %A J. Wang %A B. H. Calhoun %B Transactions on VLSI Systems (TVLSI) %G eng %1 WangCalhoun_TVLSI_modeling_2011.pdf|WangCalhoun_TVLSI_modeling_2011.pdf %0 Journal Article %J IEEE Transactions of VLSI Systems (TVLSI) %D 2011 %T Non-Random Device Mismatch Considerations in Nanoscale SRAM %A R. W. Mann %A T. B. Hook %A P. Nguyen %A B. H. Calhoun %B IEEE Transactions of VLSI Systems (TVLSI) %G eng %0 Generic %D 2011 %T A Programmable Multi-channel Sub-threshold FIR Filter for a Body Area Sensor Node %A A.M. Klinefelter %A B. H. Calhoun %G eng %0 Conference Paper %B Design Automation and Test in Europe (DATE) %D 2011 %T Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication %A B. H. Meyer %A K. Skadron %A N. George %A B. H. Calhoun %A J. Lach %B Design Automation and Test in Europe (DATE) %8 03/2011 %G eng %1 Meyer_DATE2011_paper.PDF|Meyer_DATE2011_paper.PDF %0 Generic %D 2011 %T A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm %A Y. Yu %A J. Huang %A S. Khanna %A B. H. Calhoun %A J. Lach %A A. Shelat %A D. Evans %C 2011 Workshop on RFID Security %G eng %0 Journal Article %J Transactions on VLSI Systems (TVLSI) %D 2011 %T Tracking On-Chip Age Using Distributed, Embedded Sensors %A Stuart N. Wooters %A A. C. Cabe %A Z. Qi %A J. Wang %A R. W. Mann %A B. H. Calhoun %A M. R. Stan %A Travis N. Blalock %B Transactions on VLSI Systems (TVLSI) %G eng %0 Journal Article %J ACM / SIGDA Newsletter %D 2011 %T What is a Body Sensor Network? %A B. H. Calhoun %A J. Lach %B ACM / SIGDA Newsletter %V 41 %8 10/2011 %G eng %1 CalhounLach_WhatIs_Sigda_2011.pdf|CalhounLach_WhatIs_Sigda_2011.pdf %0 Conference Paper %B ISQED %D 2010 %T Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation %A S. Nalam %A V. Chandra %A C. Pietrzyk %A R. C. Aitken %A B. H. Calhoun %B ISQED %P 139-146 %G eng %1 Nalam_ISQED2010_paper.pdf|Nalam_ISQED2010_paper.pdf %0 Conference Paper %B IEEE Sensors %D 2010 %T A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing %A J.B. Stocking %A W.C. Eberhardt %A Y.A. Shakhsheer %A J.R. Paulus %A M. Appleby %A B. H. Calhoun %B IEEE Sensors %G eng %0 Journal Article %J Journal of Solid State Electronics %D 2010 %T Impact of circuit assist methods on margin and performance in 6T SRAM %A R. W. Mann %A J. Wang %A S. Nalam %A S. Khanna %A G. Braceras %A H. Pilo %A B. H. Calhoun %K Process variation %K Read assist %K Scaling %K SNM %K SRAM %K Vmin %K Write assist %K Write margin %K Yield %B Journal of Solid State Electronics %I Elsevier %V 54 %P 1398-1407 %8 11/2010 %G eng %U http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TY5-50GTRCY-1&_user=709071&_coverDate=11%2F30%2F2010&_rdoc=1&_fmt=high&_orig=search&_sort=d&_docanchor=&view=c&_acct=C000039638&_version=1&_urlVersion=0&_userid=709071&md5=2d0ef46bf2e72b91309a5c16 %1 Mann_SSE2010.pdf|Mann_SSE2010.pdf %& 1398 %0 Conference Paper %B CICC %D 2010 %T Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress %A Jiajing Wang %A Nalam, Satyanand %A Jerry Qi %A R. W. Mann %A Mircea Stan %A B. H. Calhoun %B CICC %C San Jose, CA %8 09/2010 %G eng %1 wang_cicc2010_paper.pdf|wang_cicc2010_paper.pdf %0 Conference Paper %B GOMAC Tech %D 2010 %T REESES: Rapid Efficient Energy Scalable ElectronicS %A B. H. Calhoun %A S. Arrabi %A S. Khanna %A Y. Shakhsheer %A K. Craig %A J. Ryan %A J. Lach %B GOMAC Tech %8 03/2010 %G eng %0 Conference Paper %B Design Automation Conference (DAC) %D 2010 %T Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers %A S. Nalam %A M. Bhargava %A K. Mai %A B. H. Calhoun %B Design Automation Conference (DAC) %P 138-143 %8 06/2010 %G eng %1 Nalam_DAC2010_paper.pdf|Nalam_DAC2010_paper.pdf %0 Conference Paper %B CICC %D 2009 %T Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T %A S. Nalam %A B. H. Calhoun %B CICC %P 709-712 %G eng %1 Nalam_CICC09_paper.pdf|Nalam_CICC09_paper.pdf %0 Journal Article %J Computer %D 2009 %T Body Area Sensor Networks: Challenges and Opportunities %A Hanson, M.A. %A Powell Jr, H.C. %A Barth, A.T. %A Ringgenberg, K. %A B. H. Calhoun %A Aylor, J.H. %A J. Lach %B Computer %I IEEE Computer Society Press Los Alamitos, CA, USA %V 42 %P 58–65 %8 1/2009 %G eng %1 Hanson_Computer2009.pdf|Hanson_Computer2009.pdf %0 Conference Paper %B TECHCON %D 2009 %T An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization %A M. Bhargava %A S. Nalam %A B. H. Calhoun %A K. Mai %X SRAM design in scaled technologies increasingly requires circuit innovations such as read/write assist techniques or alternative bitcells to ensure even basic functionality. However, the lack of a quick mechanism for understanding the impact of these circuit level changes on system level metrics makes accurate assessments of new circuit techniques difficult. Thus, we introduce Virtual Prototyper (ViPro), a tool that helps circuit designers explore this large design space by rapidly generating optimized virtual prototypes of complete SRAM macros. ViPro does this by allowing SRAM component specification with varying levels of detail – from ‘black-box’ descriptions to complete netlists – and by incorporating those components into a hierarchical model that captures circuit and architectural features of the SRAM to optimize a complete prototype. SRAM designers can use ViPro to generate base-case prototypes, which provide starting points for design space exploration, or to assess the impact of a low level circuit innovation on the overall SRAM design. %B TECHCON %G eng %1 Bhargava_TECHCON09_paper.pdf|Bhargava_TECHCON09_paper.pdf %0 Conference Paper %B International Symposium on Circuits and Systems %D 2009 %T Sub-threshold Circuit Design with Shrinking CMOS Devices %A B. H. Calhoun %A S. Khanna %A Mann, R. %A J. Wang %B International Symposium on Circuits and Systems %8 3/24/2009 %G eng %1 Calhoun_ISCAS2009subvt_slides.pdf|Calhoun_ISCAS2009subvt_slides.pdf %0 Conference Paper %B ICCD %D 2009 %T A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes %A S. Nalam %A M. Bhargava %A Ringgenberg, K. %A K. Mai %A B. H. Calhoun %B ICCD %P 523-528 %G eng %1 Nalam_ICCD2009_slides.pdf|Nalam_ICCD2009_slides.pdf %0 Conference Paper %B International Symposium on Low Power Electronics and Design %D 2008 %T Analyzing Static and Dynamic Write Margin for Nanometer SRAMs %A J. Wang %A S. Nalam %A B. H. Calhoun %B International Symposium on Low Power Electronics and Design %P 129-134 %8 08/2008 %G eng %1 Wang_ISLPED2008_paper.pdf|Wang_ISLPED2008_paper.pdf