TY - CONF T1 - A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors T2 - 2017 IEEE Custom Integrated Circuits Conference (CICC) Y1 - 2017 A1 - A. Banerjee A1 - N. Liu A1 - H. N. Patel A1 - B. H. Calhoun ED - J. Poulton ED - C. T. Gray JF - 2017 IEEE Custom Integrated Circuits Conference (CICC) CY - Austin, TX, 2017 U1 - CICC2017_SRAM.pdf|Banerjee_CICC2017.pdf ER - TY - JOUR T1 - A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications JF - J. Low Power Electron. Appl. (JLPEA) Y1 - 2016 A1 - D. Akella Kamakshi A1 - A. Shrivastava A1 - B. H. Calhoun VL - 6 U1 - A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications.pdf|A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications.pdf ER - TY - JOUR T1 - A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply JF - IEEE Journal of Solid-State Circuits (JSSC) Y1 - 2016 A1 - A. Shrivastava A1 - Akella, D. A1 - B. H. Calhoun VL - 51 U1 - A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply.pdf|A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply.pdf ER - TY - CONF T1 - A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS T2 - IEEE International Solid-State Circuits Conference (ISSCC) Y1 - 2016 A1 - Roberts, N. E. A1 - K. Craig A1 - A. Shrivastava A1 - S. N. Wooters A1 - Y. Shakhsheer A1 - B. H. Calhoun A1 - Wentzloff, D. D. JF - IEEE International Solid-State Circuits Conference (ISSCC) U1 - A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS.pdf|A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS.pdf ER - TY - JOUR T1 - A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications JF - Journal of Low Power Electronics and Applications (JLPEA) Y1 - 2016 A1 - Akella, D. A1 - A. Shrivastava A1 - C. Duan A1 - B. H. Calhoun VL - 6 U1 - A 36nW, 7 ppmoC Fully On-Chip Clock Source System for Ultra-Low Power Applications.pdf|A 36nW, 7 ppmoC Fully On-Chip Clock Source System for Ultra-Low Power Applications.pdf ER - TY - CONF T1 - A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic T2 - European Solid State Circuits Conference (ESSCIRC) Y1 - 2016 A1 - H. N. Patel A1 - Roy, A. A1 - F. B. Yahya A1 - N. Liu A1 - K. Kumeno A1 - M. Yasuda A1 - A. Harada A1 - T. Ema A1 - B. H. Calhoun JF - European Solid State Circuits Conference (ESSCIRC) U1 - A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf|A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf ER - TY - JOUR T1 - A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs JF - J. Low Power Electron. Appl. (JLPEA) Y1 - 2016 A1 - Y. Huang A1 - A. Shrivastava A1 - L. Barnes A1 - B. H. Calhoun VL - 6 U1 - A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs.pdf|A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs.pdf ER - TY - CONF T1 - Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool T2 - IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Y1 - 2016 A1 - N. Liu A1 - B. H. Calhoun JF - IEEE Computer Society Annual Symposium on VLSI (ISVLSI) U1 - ISVLSI-2016_Poster_ViPro.pdf|ISVLSI-2016_Poster_ViPro.pdf ER - TY - JOUR T1 - Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array JF - Bioinspiration and Biomimetics Y1 - 2016 A1 - W. Eberhardt A1 - B. Wakefield A1 - C. Casey A1 - C. Murphy A1 - B. H. Calhoun A1 - C. Reichmuth U1 - Development of an artificial sensor for hydrodynamic detection inspired by a seal\textquoterights whisker array.pdf| ER - TY - CONF T1 - Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks T2 - ASYNC Y1 - 2016 A1 - D. Kamakshi A1 - M. Fojtik A1 - B. Khailany A1 - S. Kudva A1 - Y. Zhou A1 - B. H. Calhoun JF - ASYNC U1 - Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks.pdf|Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks.pdf ER - TY - JOUR T1 - A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs JF - J. Low Power Electron. Appl. (JLPEA) Y1 - 2016 A1 - F. Yahya A1 - H. Patel A1 - Boley, J. A1 - A. Banerjee A1 - B. H. Calhoun VL - 6 U1 - A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf|A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf ER - TY - CONF T1 - A Tunnel FET Design for High-Current, 120 mV Operation T2 - IEDM Y1 - 2016 A1 - P. Long A1 - J. Z. Huang A1 - M. Povolotskyi A1 - D. Verreck A1 - J. Charles A1 - T. Kubis A1 - G. Klimeck A1 - M. J.W. Rodwell A1 - B. H. Calhoun JF - IEDM ER - TY - JOUR T1 - A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting with 220mV Cold-Start and -14.5dBm, 915MHz RF Kick-Start JF - IEEE Journal of Solid-State Circuits (JSSC) Y1 - 2015 A1 - A. Shrivastava A1 - Roberts, N. E. A1 - O. U. Khan A1 - Wentzloff, D. D. A1 - B. H. Calhoun VL - 50 ER - TY - CONF T1 - A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs T2 - IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Y1 - 2015 A1 - Y. Huang A1 - A. Shrivastava A1 - B. H. Calhoun JF - IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ER - TY - CONF T1 - A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems T2 - EEE International Solid-State Circuits Conference (ISSCC) Y1 - 2015 A1 - A. Shrivastava A1 - K. Craig A1 - N. Roberts A1 - Wentzloff, D. D. A1 - B. H. Calhoun JF - EEE International Solid-State Circuits Conference (ISSCC) ER - TY - CONF T1 - Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications T2 - International Symposium on Circuits and Systems (ISCAS) Y1 - 2015 A1 - Klinefelter, A. A1 - J. Ryan A1 - Tschanz, J. A1 - B. H. Calhoun JF - International Symposium on Circuits and Systems (ISCAS) ER - TY - CONF T1 - Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset T2 - International Symposium on Quality Electronic Design Y1 - 2015 A1 - Boley, J. A1 - B. H. Calhoun JF - International Symposium on Quality Electronic Design ER - TY - CONF T1 - Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors T2 - GOMACTech Y1 - 2015 A1 - Y. Shakhsheer A1 - A. Shrivastava A1 - N. Roberts A1 - K. Craig A1 - S. Wooters A1 - Wentzloff, D. D. A1 - B. H. Calhoun JF - GOMACTech ER - TY - CONF T1 - Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT T2 - HOT Chips Y1 - 2015 A1 - B. H. Calhoun A1 - Wentzloff, D. D. JF - HOT Chips ER - TY - CONF T1 - A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting T2 - IEEE Custom Integrated Circuits Conference (CICC) Y1 - 2014 A1 - A. Shrivastava A1 - D. Wentzloff A1 - B. H. Calhoun JF - IEEE Custom Integrated Circuits Conference (CICC) U1 - 2014_Aatmesh_CICC.pdf|2014_Aatmesh_CICC.pdf ER - TY - CONF T1 - A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages T2 - Symposium on VLSI Circuits Y1 - 2014 A1 - A. Shrivastava A1 - Y. K. Ramadass A1 - S. Khanna A1 - S. Bartling A1 - B. H. Calhoun JF - Symposium on VLSI Circuits U1 - 06858364.pdf ER - TY - JOUR T1 - 39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation JF - Journal of Low Power Electronics and Applications (JLPEA) Y1 - 2014 A1 - J.Bolus A1 - B. H. Calhoun A1 - T.Blalock VL - 4 ER - TY - CONF T1 - Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits T2 - International Symposium on Quality Electronic Design (ISQED) Y1 - 2014 A1 - Y. Zhang A1 - B. H. Calhoun JF - International Symposium on Quality Electronic Design (ISQED) ER - TY - CONF T1 - Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems T2 - International Symposium on Field-Programmable Custom Computing Machines (FCCM) Y1 - 2014 A1 - S. Arrabi A1 - D. Moore A1 - L. Wang A1 - K. Skadron A1 - B. H. Calhoun JF - International Symposium on Field-Programmable Custom Computing Machines (FCCM) U1 - 06861633.pdf|06861633.pdf ER - TY - CONF T1 - LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications T2 - GOMAC Tech Y1 - 2014 A1 - J. J. Granacki A1 - B. H. Calhoun A1 - A. R. Dasu A1 - M. Jagasivamani A1 - L. McIlrath A1 - M. Fritze JF - GOMAC Tech ER - TY - CONF T1 - Modeling SRAM Dynamic VMIN T2 - International Conference on IC Design and Technology (ICICDT) Y1 - 2014 A1 - Boley, J. A1 - V. Chandra A1 - R. Aitken A1 - B. H. Calhoun JF - International Conference on IC Design and Technology (ICICDT) ER - TY - CONF T1 - Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories T2 - VLSI Design Conference Y1 - 2014 A1 - S. Khanna A1 - S. V. Nalam A1 - B. H. Calhoun JF - VLSI Design Conference U1 - 06733120.pdf|06733120.pdf ER - TY - CONF T1 - A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs T2 - S3S Conference Y1 - 2014 A1 - Klinefelter, A. A1 - B. H. Calhoun JF - S3S Conference CY - Monterey, CA U1 - s3s_final_klinefelter_0.pdf|s3s_final_klinefelter_0.pdf ER - TY - CONF T1 - A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs T2 - International Symposium on Quality Electronic Design (ISQED) Y1 - 2014 A1 - A. Banerjee A1 - M. Sinangil A1 - J. Poulton A1 - C. T. Gray A1 - B. H. Calhoun JF - International Symposium on Quality Electronic Design (ISQED) U1 - 06783299.pdf|06783299.pdf ER - TY - CONF T1 - Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM T2 - Design Automation Conference (DAC) Y1 - 2014 A1 - P. Beshay A1 - V. Chandra A1 - R. Aitken A1 - B. H. Calhoun JF - Design Automation Conference (DAC) ER - TY - JOUR T1 - An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications JF - Journal of Low Power Electronics and Applications (JLPEA) Y1 - 2014 A1 - A. Banerjee A1 - B. H. Calhoun VL - 4 ER - TY - JOUR T1 - Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin JF - Journal of Low Power Electronics and Applications Y1 - 2012 A1 - James Boley A1 - Jiajing Wang A1 - B. H. Calhoun U1 - Boley_JLPEA2012.pdf|Boley_JLPEA2012.pdf ER - TY - JOUR T1 - Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN JF - Journal of Low Power Electronics and Applications (JLPEA) Y1 - 2012 A1 - Boley, J. A1 - J. Wang A1 - B. H. Calhoun VL - 2 U1 - Boley_JLPEA2012.pdf|Boley_JLPEA2012.pdf ER - TY - Generic T1 - A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS T2 - Custom Integrated Circuits Conference Y1 - 2012 A1 - Y. Shakhsheer A1 - Y. Zhang A1 - B. Otis A1 - B. H. Calhoun JF - Custom Integrated Circuits Conference CY - San Jose U1 - Shakhsheer_CICC2012.pdf|Shakhsheer_CICC2012.pdf ER - TY - JOUR T1 - Tracking On-Chip Age Using Distributed, Embedded Sensors JF - Transactions on VLSI Systems (TVLSI) Y1 - 2012 A1 - S. N. Wooters A1 - A. C. Cabe A1 - Z. Qi A1 - J. Wang A1 - R. W. Mann A1 - B. H. Calhoun A1 - M. R. Stan A1 - T. N. Blalock VL - 20 ER - TY - CONF T1 - A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V T2 - Custom Integrated Circuits Conference Y1 - 2011 A1 - Y. Shakhsheer A1 - S. Khanna A1 - K. Craig A1 - S. Arrabi A1 - J. Lach A1 - B. H. Calhoun JF - Custom Integrated Circuits Conference CY - San Jose U1 - PDVS_CICC2011_Final.pdf|PDVS_CICC2011_Final.pdf ER - TY - CONF T1 - An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal T2 - Internation Symposium on Lower Power Electronics and Design (ISLPED) Y1 - 2011 A1 - J. F. Ryan A1 - S. Khanna A1 - B. H. Calhoun JF - Internation Symposium on Lower Power Electronics and Design (ISLPED) ER - TY - ABST T1 - Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin Y1 - 2011 A1 - Boley, J. A1 - B. H. Calhoun A1 - J. Wang ER - TY - CONF T1 - A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability T2 - IEEE Sensors Y1 - 2011 A1 - W.C. Eberhardt A1 - Y.A. Shakhsheer A1 - B. H. Calhoun JF - IEEE Sensors CY - Limrick, Ireland U1 - Eberhardt_IEEESensors2011.pdf|Eberhardt_IEEESensors2011.pdf ER - TY - Generic T1 - Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy T2 - CASES Y1 - 2011 A1 - B. H. Meyer A1 - B. H. Calhoun A1 - J. C. Lach A1 - K. Skadron JF - CASES ER - TY - CONF T1 - Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM T2 - Design Automation and Test Europe (DATE) Y1 - 2011 A1 - S. Nalam A1 - V. Chandra A1 - R. C. Aitken A1 - B. H. Calhoun JF - Design Automation and Test Europe (DATE) U1 - Nalam_DATE2011_paper.PDF|Nalam_DATE2011_paper.PDF ER - TY - JOUR T1 - Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations JF - Transactions on VLSI Systems (TVLSI) Y1 - 2011 A1 - J. Wang A1 - B. H. Calhoun U1 - WangCalhoun_TVLSI_modeling_2011.pdf|WangCalhoun_TVLSI_modeling_2011.pdf ER - TY - JOUR T1 - Non-Random Device Mismatch Considerations in Nanoscale SRAM JF - IEEE Transactions of VLSI Systems (TVLSI) Y1 - 2011 A1 - R. W. Mann A1 - T. B. Hook A1 - P. Nguyen A1 - B. H. Calhoun ER - TY - ABST T1 - A Programmable Multi-channel Sub-threshold FIR Filter for a Body Area Sensor Node Y1 - 2011 A1 - A.M. Klinefelter A1 - B. H. Calhoun ER - TY - CONF T1 - Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication T2 - Design Automation and Test in Europe (DATE) Y1 - 2011 A1 - B. H. Meyer A1 - K. Skadron A1 - N. George A1 - B. H. Calhoun A1 - J. Lach JF - Design Automation and Test in Europe (DATE) U1 - Meyer_DATE2011_paper.PDF|Meyer_DATE2011_paper.PDF ER - TY - ABST T1 - A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm Y1 - 2011 A1 - Y. Yu A1 - J. Huang A1 - S. Khanna A1 - B. H. Calhoun A1 - J. Lach A1 - A. Shelat A1 - D. Evans CY - 2011 Workshop on RFID Security ER - TY - JOUR T1 - Tracking On-Chip Age Using Distributed, Embedded Sensors JF - Transactions on VLSI Systems (TVLSI) Y1 - 2011 A1 - Stuart N. Wooters A1 - A. C. Cabe A1 - Z. Qi A1 - J. Wang A1 - R. W. Mann A1 - B. H. Calhoun A1 - M. R. Stan A1 - Travis N. Blalock ER - TY - JOUR T1 - What is a Body Sensor Network? JF - ACM / SIGDA Newsletter Y1 - 2011 A1 - B. H. Calhoun A1 - J. Lach VL - 41 U1 - CalhounLach_WhatIs_Sigda_2011.pdf|CalhounLach_WhatIs_Sigda_2011.pdf ER - TY - CONF T1 - Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation T2 - ISQED Y1 - 2010 A1 - S. Nalam A1 - V. Chandra A1 - C. Pietrzyk A1 - R. C. Aitken A1 - B. H. Calhoun JF - ISQED U1 - Nalam_ISQED2010_paper.pdf|Nalam_ISQED2010_paper.pdf ER - TY - CONF T1 - A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing T2 - IEEE Sensors Y1 - 2010 A1 - J.B. Stocking A1 - W.C. Eberhardt A1 - Y.A. Shakhsheer A1 - J.R. Paulus A1 - M. Appleby A1 - B. H. Calhoun JF - IEEE Sensors ER - TY - JOUR T1 - Impact of circuit assist methods on margin and performance in 6T SRAM JF - Journal of Solid State Electronics Y1 - 2010 A1 - R. W. Mann A1 - J. Wang A1 - S. Nalam A1 - S. Khanna A1 - G. Braceras A1 - H. Pilo A1 - B. H. Calhoun KW - Process variation KW - Read assist KW - Scaling KW - SNM KW - SRAM KW - Vmin KW - Write assist KW - Write margin KW - Yield PB - Elsevier VL - 54 UR - http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TY5-50GTRCY-1&_user=709071&_coverDate=11%2F30%2F2010&_rdoc=1&_fmt=high&_orig=search&_sort=d&_docanchor=&view=c&_acct=C000039638&_version=1&_urlVersion=0&_userid=709071&md5=2d0ef46bf2e72b91309a5c16 N1 - published U1 - Mann_SSE2010.pdf|Mann_SSE2010.pdf ER - TY - CONF T1 - Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress T2 - CICC Y1 - 2010 A1 - Jiajing Wang A1 - Nalam, Satyanand A1 - Jerry Qi A1 - R. W. Mann A1 - Mircea Stan A1 - B. H. Calhoun JF - CICC CY - San Jose, CA U1 - wang_cicc2010_paper.pdf|wang_cicc2010_paper.pdf ER - TY - CONF T1 - REESES: Rapid Efficient Energy Scalable ElectronicS T2 - GOMAC Tech Y1 - 2010 A1 - B. H. Calhoun A1 - S. Arrabi A1 - S. Khanna A1 - Y. Shakhsheer A1 - K. Craig A1 - J. Ryan A1 - J. Lach JF - GOMAC Tech ER - TY - CONF T1 - Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers T2 - Design Automation Conference (DAC) Y1 - 2010 A1 - S. Nalam A1 - M. Bhargava A1 - K. Mai A1 - B. H. Calhoun JF - Design Automation Conference (DAC) U1 - Nalam_DAC2010_paper.pdf|Nalam_DAC2010_paper.pdf ER - TY - CONF T1 - Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T T2 - CICC Y1 - 2009 A1 - S. Nalam A1 - B. H. Calhoun JF - CICC U1 - Nalam_CICC09_paper.pdf|Nalam_CICC09_paper.pdf ER - TY - JOUR T1 - Body Area Sensor Networks: Challenges and Opportunities JF - Computer Y1 - 2009 A1 - Hanson, M.A. A1 - Powell Jr, H.C. A1 - Barth, A.T. A1 - Ringgenberg, K. A1 - B. H. Calhoun A1 - Aylor, J.H. A1 - J. Lach PB - IEEE Computer Society Press Los Alamitos, CA, USA VL - 42 U1 - Hanson_Computer2009.pdf|Hanson_Computer2009.pdf ER - TY - CONF T1 - An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization T2 - TECHCON Y1 - 2009 A1 - M. Bhargava A1 - S. Nalam A1 - B. H. Calhoun A1 - K. Mai AB - SRAM design in scaled technologies increasingly requires circuit innovations such as read/write assist techniques or alternative bitcells to ensure even basic functionality. However, the lack of a quick mechanism for understanding the impact of these circuit level changes on system level metrics makes accurate assessments of new circuit techniques difficult. Thus, we introduce Virtual Prototyper (ViPro), a tool that helps circuit designers explore this large design space by rapidly generating optimized virtual prototypes of complete SRAM macros. ViPro does this by allowing SRAM component specification with varying levels of detail – from ‘black-box’ descriptions to complete netlists – and by incorporating those components into a hierarchical model that captures circuit and architectural features of the SRAM to optimize a complete prototype. SRAM designers can use ViPro to generate base-case prototypes, which provide starting points for design space exploration, or to assess the impact of a low level circuit innovation on the overall SRAM design. JF - TECHCON U1 - Bhargava_TECHCON09_paper.pdf|Bhargava_TECHCON09_paper.pdf ER - TY - CONF T1 - Sub-threshold Circuit Design with Shrinking CMOS Devices T2 - International Symposium on Circuits and Systems Y1 - 2009 A1 - B. H. Calhoun A1 - S. Khanna A1 - Mann, R. A1 - J. Wang JF - International Symposium on Circuits and Systems U1 - Calhoun_ISCAS2009subvt_slides.pdf|Calhoun_ISCAS2009subvt_slides.pdf ER - TY - CONF T1 - A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes T2 - ICCD Y1 - 2009 A1 - S. Nalam A1 - M. Bhargava A1 - Ringgenberg, K. A1 - K. Mai A1 - B. H. Calhoun JF - ICCD U1 - Nalam_ICCD2009_slides.pdf|Nalam_ICCD2009_slides.pdf ER - TY - CONF T1 - Analyzing Static and Dynamic Write Margin for Nanometer SRAMs T2 - International Symposium on Low Power Electronics and Design Y1 - 2008 A1 - J. Wang A1 - S. Nalam A1 - B. H. Calhoun JF - International Symposium on Low Power Electronics and Design U1 - Wang_ISLPED2008_paper.pdf|Wang_ISLPED2008_paper.pdf ER -