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Author Title Type [ Year(Desc)]
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2003
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., β€œDesign Methodology for Fine-Grained Leakage Control in MTCMOS”, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
2004
B. H. Calhoun and Chandrakasan, A., β€œCharacterizing and Modeling Minimum Energy Operation for Subthreshold Circuits”, in International Symposium on Low Power Electronics and Design, 2004, pp. 90-95.
E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., β€œDesign Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., β€œDesign Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.
B. H. Calhoun, Wang, A., and Chandrakasan, A., β€œDevice Sizing for Minimum Energy Operation in Subthreshold Circuits”, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., β€œA Leakage Reduction Methodology for Distributed MTCMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.
B. H. Calhoun and Chandrakasan, A., β€œStandby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.
2006
B. H. Calhoun and Chandrakasan, A., β€œA 256kb Sub-threshold SRAM in 65nm CMOS”, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., β€œLow Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
A. P. Chandrakasan, Verma, N., Kwong, J., Daly, D., Ickes, N., Finchelstein, D., and Calhoun, B. H., β€œMicropower Wireless Sensors”, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.
B. H. Calhoun, ,, and Chandrakasan, A., β€œPower Gating and Dynamic Voltage Scaling”, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
B. H. Calhoun and Chandrakasan, A., β€œStatic Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., β€œSub-threshold Design: The Challenges of Minimizing Circuit Energy”, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
B. H. Calhoun and Chandrakasan, A., β€œUltra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
2008
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., β€œDigital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.

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