Publications
“A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications”, in Symposium on VLSI Circuits, 2013.
, “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
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“Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)
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“Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2023.
, “A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)
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“Body Area Sensor Networks: Challenges and Opportunities”, Computer, vol. 42, pp. 58–65, 2009.
, “A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.
, “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A 2.6-μW Sub-threshold Mixed-signal ECG SoC”, in Symposium on VLSI Circuits, 2009.
, “Mobile Health Monitoring Through Biotelemetry”, in Bodynets, 2009.
, “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
, “A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs”, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
, “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros”, in IEEE Custom Integrated Circuits Conference (CICC), 2021.
kamineni2021.pdf (9.26 MB)
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“AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells”, in Design, Automation and Test in Europe Conference (DATE), 2023, 2023.
AuxcellGen-A Framework for Autonomous Generation of Analog and Memory Unit Cells.pdf (3.37 MB)
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“Serial Sub-threshold Circuits for Ultra-Low-Power Systems”, in International Symposium on Low Power Electronics and Design, 2009.
, “Stepped Supply Voltage Switching for Energy Constrained Systems”, in ISQED, 2011.
, “Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories”, in VLSI Design Conference, 2014.
, “A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC”, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, p. 941, 2012.
, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
, “Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications”, in International Symposium on Circuits and Systems (ISCAS), 2015.
, , “A 6.45 μW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios”, in ISSCC, San Francisco, CA, 2015.
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