Publications
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, “A 1pJ/Bit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks”, in 2023 IEEE Biomedical Circuits and Systems Conference, 2023.
A 1pJbit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks.pdf (2.54 MB)
A 1pJbit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks.pdf (2.54 MB), “A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization”, in IEEE International Solid-State Circuits Conference (ISSCC), 2022. A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB)
A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB), “A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization”, in IEEE International Solid-State Circuits Conference (ISSCC), 2022. A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB)
A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB), “A 184 nW, -78.3 dBm Sensitivity Antenna-Coupled Supply, Temperature, and Interference-Robust Wake-up Receiver at 4.9 GHz”, IEEE Transactions on Microwave Theory and Techniques, 2022.
, “A 10-Channel, 1.2 µW, Reconfigurable Capacitanceto-Digital Converter for Low-Power, Wearable Healthcare Applications”, in 2023 IEEE Biomedical Circuits and Systems Conference, 2023.
, “A -108dBm Sensitivity, -28dB SIR, 130nW to 41μW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver”, in IEEE Custom Integrated Circuits Conference (CICC), 2020.
, “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR”, in IEEE Custom Integrated Circuits Conference (CICC), 2023.
, “A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications”, IEEE Transactions on Biomedical Circuits and Systems, 2019. 08625544.pdf (3.22 MB)
08625544.pdf (3.22 MB), “A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications”, IEEE Transactions on Biomedical Circuits and Systems, 2019. 08625544.pdf (3.22 MB)
08625544.pdf (3.22 MB), “A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications”, IEEE Transactions on Biomedical Circuits and Systems, 2019. 08625544.pdf (3.22 MB)
08625544.pdf (3.22 MB), “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.
, “A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability Using a Duty-Cycled Digital Frequency-Locked Loop”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB), “A 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop”, IEEE Journal of Solid-State Circuits, 2021. A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)
A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB), “A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis”, Journal of Low Power Electronics and Applications (JLPEA), 2018.
, “A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems”, in International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.