Robust Low Power VLSI
VLSI Design Group

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2010
S. N. Wooters, Calhoun, B. H., and Blalock, T. N., “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.
J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “SRAM-Based NBTI/PBTI Sensor System Design”, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
J. Wang and Calhoun, B. H., “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs”, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs”, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.
2009
S. Jocke, Bolus, J., Wooters, S. N., Jurik, A. D., Weaver, A. F., Blalock, T. N., and Calhoun, B. H., “A 2.6-μW Sub-threshold Mixed-signal ECG SoC”, in Symposium on VLSI Circuits, 2009.
S. Jocke, Bolus, J., Wooters, S. N., Jurik, A. D., Weaver, A. F., Blalock, T. N., and Calhoun, B. H., “A 2.6-μW Sub-threshold Mixed-signal ECG SoC”, in Symposium on VLSI Circuits, 2009.
A. D. Jurik, Bolus, J., Weaver, A. F., Calhoun, B. H., and Blalock., T. N., “Mobile Health Monitoring Through Biotelemetry”, in Bodynets, 2009.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “MSN: Memory Sensor for NBTI”, in Techcon, 2009.
B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.
2008
J. Wang, Nalam, S., and Calhoun, B. H., “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
J. Wang and Calhoun, B. H., “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction”, in TECHCON, 2008.
A. Singhee, Wang, J., Calhoun, B. H., and Rutenbar, R. A., “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design”, in International Conference on VLSI Design, India, 2008, pp. 131-136.
J. Wang and Calhoun, B. H., “Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.
2007
J. F. Ryan, Wang, J., and Calhoun, B. H., “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.
J. Wang and Calhoun, B. H., “Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM”, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array”, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics”, in Proc. of GOMAC Tech, 2007.
2006
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., “Low Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
A. Wang and Calhoun, A. Chandrakas, Sub-threshold Design for Ultra Low-Power Systems. Springer, 2006.
B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., “Sub-threshold Design: The Challenges of Minimizing Circuit Energy”, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
2005
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.

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