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J. F. Ryan, Wang, J., and Calhoun, B. H., Analyzing and Modeling Process Balance for Sub-threshold Circuit Design, in GLSVLSI, 2007, pp. 275-280.
J. F. Ryan and Calhoun, B. H., Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation, in International Symposium on Quality Electronic Design, 2008, pp. 127-132.
J. F. Ryan and Calhoun, B. H., A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS, in Custom Integrated Circuits Conference (CICC), 2010.
J. F. Ryan, Khanna, S., and Calhoun, B. H., An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
A. Roy, Klinefelter, A., Yahya, F., Chen, X., Gonzalez, P., Lukas, C. J., Akella, D., Boley, J., Craig, K., Faisal, M., Oh, S., Roberts, N., Shakhsheer, Y., Shrivastava, A., Vasudevan, D., Wentzloff, D. D., and Calhoun, B., A 6.45μW Self-Powered SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems, IEEE Transactions on Biomedical Circuits and Systems, vol. 9, pp. 862-874, 2015.
A. Roy and Calhoun, B., Exploring Circuit Robustness to Power Supply Variation in Low-Voltage Latch and Register-Based Digital Systems, in IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.
A. Roy, Grossmann, P., Vitale, S., and Calhoun, B., A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
A. Roy and Calhoun, B. H., A 71% Efficient Energy Harvesting and Power Management Unit for Sub-µW Power Biomedical Applications, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.