Publications
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“A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
, “A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs”, in International Symposium on Quality Electronic Design (ISQED), 2014.
, “Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM”, in Design Automation Conference (DAC), 2014.
, “Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM”, in Design Automation Conference (DAC), 2014.
, “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
, “A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications”, in Symposium on VLSI Circuits, 2013.
, “A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node”, in VLSI Design Conference, 2013.
, “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.
, “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.
, “A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications”, 2013.
, “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers”, Journal of Low Power Electronics and Applications, 2013.
, “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
, “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.
, “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.
, “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.
, “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
, “A 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCs”, in Custom Integrated Circuits Conference, San Jose, 2012.
, “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.
, “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN”, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.
, “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.
, “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.
, “A Charge Pump Based Receiver Circuit for a Voltage Scaled Interconnect”, in International Symposium on Low Power Electronics and Design, 2012.
, “A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS”, Custom Integrated Circuits Conference. San Jose, 2012.
, “Dark vs. Dim Silicon and Near-Threshold Computing”, in Dark Silicon Workshop (DaSi), 2012.
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