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Journal Article
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., A Leakage Reduction Methodology for Distributed MTCMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.
D. S. Truesdell, Ahmed, S. Z., Ghosh, A. W., and Calhoun, B. H., Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.PDF icon Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
B. H. Calhoun, Wang, A., and Chandrakasan, A., Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.
S. Z. Ahmed, Tan, Y., Truesdell, D. S., Calhoun, B. H., and Ghosh, A., Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance, Journal of Applied Physics, 2018.
S. Li, Roy, A., and Calhoun, B. H., A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated Maximum-Power-Point Tracking, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
A. Klinefelter, Zhang, Y., Otis, B., and Calhoun, B. H., A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, p. 941, 2012.
D. S. Truesdell and Calhoun, B. H., A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range, IEEE Solid-State Circuits Letters (SSCL), 2020.PDF icon A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
B. H. Calhoun and Chandrakasan, A., Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.
B. H. Calhoun and Chandrakasan, A., Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
X. Liu, Calhoun, B. H., and Li, S., A Sub-nW 93% Peak Efficiency Buck Converter with Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control, IEEE Journal of Solid-State Circuits, (invited paper), 2022.PDF icon A SubnW 93 Peak Efficiency Buck Converter With Wide Dynamic Range Fast DVFS and Asynchronous Load Transient Control.pdf (3.94 MB)
X. Liu, Kamineni, S., Breiholz, J., Calhoun, B. H., and Li, S., A Sub-µW Energy-Performance-Aware IoT SoC with a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization, IEEE Journal of Solid-State Circuits, 2024.PDF icon A_Sub-_mu_W_Energy-Performance-Aware_IoT_SoC_With_a_Triple_Mode_Power_Management_Unit_for_System_Performance_Scaling_Fast_DVFS_and_Energy_Minimization.pdf (7.38 MB)
J. Wang and Calhoun, B. H., Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.
F. B. Yahya, Lukas, C. J., and Calhoun, B. H., A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things, Journal of Low Power Electronics & Applications, 2018.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
A. Mallick, Bashar, M. K., Truesdell, D. S., Calhoun, B. H., Joshi, S., and Shukla, N., Using synchronized oscillators to compute the maximum independent set, Nature Communications, 2020.
J. Boley, Beshay, P., and Calhoun, B. H., Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization, Transactions of Very Large Scale Integration Systems, 2015.

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