Publications
] , “Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry”, in Subthreshold Microelectronics Conference, 2012.
, “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
, “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms”, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
, “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.
, “Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors”, in GOMACTech, 2015.
, “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics”, in Proc. of GOMAC Tech, 2007.
, “Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS”, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
, “An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches”, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
, “Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT”, in HOT Chips, 2015.
, “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
, “Using island-style bi-directional intra-CLB routing in low-power FPGAs”, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
, “Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy”, CASES. 2011.
, “A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS”, Custom Integrated Circuits Conference. San Jose, 2012.
, “FGC: A Tool-flow for Generating and Configuring Custom FPGAs”, Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, Monterey, CA, 2018.
, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
, “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis”, Journal of Low Power Electronics and Applications (JLPEA), 2018.
, “A 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop”, IEEE Journal of Solid-State Circuits, 2021.
A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)
A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB), “A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability”, IEEE Solid-State Circuits Letters (SSCL), 2019. A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)