Publications
“Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.
, “An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction”, Transactions on VLSI Systems (TVLSI), 2011.
, “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.
, “SRAM-Based NBTI/PBTI Sensor System Design”, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
, “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs”, in Solid State Circuits Technologies, INTECH, 2010.
, “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs”, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.
, “MSN: Memory Sensor for NBTI”, in Techcon, 2009.
, “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction”, in TECHCON, 2008.
, “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design”, in International Conference on VLSI Design, India, 2008, pp. 131-136.
, “Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.
, “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.
, “Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM”, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.
, “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array”, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
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