Robust Low Power VLSI
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P. Beshay, Ryan, J. F., and Calhoun, B. H., “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers”, Journal of Low Power Electronics and Applications, 2013.
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
X. Liu, Agrawal, A., Tanaka, A., and Calhoun, B. H., “Distributed Energy Harvesting and Power Management Units for Self-Powered In-Fabric Sensing Networks”, 2024 IEEE Midwest Symposium on Circuits and Systems (MWSCAS), invited paper, 2024.
A. Banerjee, “A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications”, in 32nd International Conference on VLSI Design, 2019.
S. Gupta and Calhoun, B. H., “Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.PDF icon Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
S. Gupta and Calhoun, B. H., “Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.PDF icon Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)
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C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., “Energy Efficient Design for Body Sensor Nodes”, Journal of Low Power Electronics and Applications, 2011.
E. Shih, Calhoun, B. H., Cho, S. - H., and Chandrakasan, A., “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
H. Qi, Ayorinde, O., and Calhoun, B. H., “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
S. N. Wooters, Calhoun, B. H., and Blalock, T. N., “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
J. Wang and Calhoun, B. H., “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction”, in TECHCON, 2008.
J. Wang, Hoefler, A., and Calhoun, B. H., “An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction”, Transactions on VLSI Systems (TVLSI), 2011.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
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F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
O. Ayorinde, Qi, H., and Calhoun, B. H., “FGC: A Tool-flow for Generating and Configuring Custom FPGAs”, Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, Monterey, CA, 2018.
B. H. Calhoun, Ryan, J., Khanna, S., Putic, M., and Lach, J., “Flexible Circuits and Architectures for Ultra Low Power”, Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.
C. T. Murphy, W. Eberhardt, C., Calhoun, B. H., and Mann, D. A., “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception”, in Conference on the Biology of Marine Mammals, 2011.
T. Ajayi, Cherivirala, Y. K., Kwon, K., Kamineni, S., Saligane, M., Fayazi, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B. H., and Wentzloff, D. D., “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
O. Faruqe, Le, P., Lee, D., Liu, X., Abdelatty, O., Truesdell, D. S., and Calhoun, B. H., “A Fully Integrated, Custom End-to-End PPG Sensing System for Ultra-Low Power Wearables”, presented at the 2025 IEEE Intern, In Press.
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A. Mallick, Bashar, M. Khairul, Truesdell, D. S., Calhoun, B. H., Joshi, S., and Shukla, N., “Graph Coloring using Coupled Oscillator-based Dynamical Systems”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
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J. Moody, Dissanayake, A., Bishop, H. L., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
Y. Zhang and Calhoun, B. H., “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.
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D. S. Truesdell and Calhoun, B. H., “Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.

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