Publications
โAn Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gatingโ, in International Conference on Field-Programmable Technology (ICFPT 2016), Xiโan, China, 2016.
, โAn Ultra-Low-Power FPGA for IoT Applicationsโ, in S3S 2017, 2017.
, โSRAM-Based NBTI/PBTI Sensor System Designโ, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
, โPanoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Designโ, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
, โSoft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applicationsโ, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
, โA 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logicโ, in European Solid State Circuits Conference (ESSCIRC), 2016.
, โSubthreshold SRAM: Challenges, Design Decisions, and Solutionsโ, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
, โImproving Reliability and Energy Requirements of Memory in Body Sensor Networks.โ, in International Conference on VLSI Design, Kolkata, India, 2016.
, โOptimizing SRAM Bitcell Reliability and Energy for IoT Applicationsโ, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, โModeling Energy Aware Photoplethsmography for Personalized Healthcare Applicationsโ, in IEEE Transactions on Biomedical Circuits and Systems, 2022.
, โDynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMโ, in Design Automation and Test Europe (DATE), 2011.
, โA Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processesโ, in ICCD, 2009, pp. 523-528.
, โAsymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operationโ, in ISQED, 2010, pp. 139-146.
, โVirtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designersโ, in Design Automation Conference (DAC), 2010, pp. 138-143.
, , โAsymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6Tโ, in CICC, 2009, pp. 709-712.
, โEffect of Angle on Flow-Induced Vibrations of Pinniped Vibrissaeโ, PLOS One, vol. Vol. 8, No. 7, 2013.
, โFlow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Receptionโ, in Conference on the Biology of Marine Mammals, 2011.
, โInterference Robust Detector-First Near-Zero Power Wake-Up Receiverโ, IEEE Journal of Solid-State Circuits, 2019.
, โA -76dBm 7.4 nW wakeup radio with automatic offset compensationโ, in International Solid-State Circuits Conference (ISSCC), 2018.
, โA -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiverโ, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, โAn 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front Endโ, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
, โA Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumptionโ, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, โFlexible Technologies for Self-Powered Wearable Health and Environmental Sensingโ, Proceedings of the IEEE, vol. 103, pp. 665-681, 2015.
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