Publications
βAn Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gatingβ, in International Conference on Field-Programmable Technology (ICFPT 2016), Xiβan, China, 2016.
, βAn Ultra-Low-Power FPGA for IoT Applicationsβ, in S3S 2017, 2017.
, βSRAM-Based NBTI/PBTI Sensor System Designβ, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
, βPanoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Designβ, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
, βSoft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applicationsβ, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
, βA 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logicβ, in European Solid State Circuits Conference (ESSCIRC), 2016.
, βSubthreshold SRAM: Challenges, Design Decisions, and Solutionsβ, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
, βImproving Reliability and Energy Requirements of Memory in Body Sensor Networks.β, in International Conference on VLSI Design, Kolkata, India, 2016.
, βOptimizing SRAM Bitcell Reliability and Energy for IoT Applicationsβ, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, βModeling Energy Aware Photoplethsmography for Personalized Healthcare Applicationsβ, in IEEE Transactions on Biomedical Circuits and Systems, 2022.
, βDynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMβ, in Design Automation and Test Europe (DATE), 2011.
, βA Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processesβ, in ICCD, 2009, pp. 523-528.
, βAsymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operationβ, in ISQED, 2010, pp. 139-146.
, βVirtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designersβ, in Design Automation Conference (DAC), 2010, pp. 138-143.
, , βAsymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6Tβ, in CICC, 2009, pp. 709-712.
, βEffect of Angle on Flow-Induced Vibrations of Pinniped Vibrissaeβ, PLOS One, vol. Vol. 8, No. 7, 2013.
, βFlow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Receptionβ, in Conference on the Biology of Marine Mammals, 2011.
, βInterference Robust Detector-First Near-Zero Power Wake-Up Receiverβ, IEEE Journal of Solid-State Circuits, 2019.
, βA -76dBm 7.4 nW wakeup radio with automatic offset compensationβ, in International Solid-State Circuits Conference (ISSCC), 2018.
, βA -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiverβ, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, βAn 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front Endβ, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
, βA Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumptionβ, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, βFlexible Technologies for Self-Powered Wearable Health and Environmental Sensingβ, Proceedings of the IEEE, vol. 103, pp. 665-681, 2015.
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