Robust Low Power VLSI
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B. H. Calhoun and Lach, J., “What is a Body Sensor Network?”, ACM / SIGDA Newsletter, vol. 41, 2011.
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J. Boley, Beshay, P., and Calhoun, B., “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
J. Boley, Beshay, P., and Calhoun, B. H., “Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization”, Transactions of Very Large Scale Integration Systems, 2015.
S. Nalam, Bhargava, M., Mai, K., and Calhoun, B. H., “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
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A. Mallick, Bashar, M. K., Truesdell, D. S., Calhoun, B. H., Joshi, S., and Shukla, N., “Using synchronized oscillators to compute the maximum independent set”, Nature Communications, 2020.
O. Ayorinde, Qi, H., Huang, Y., and Calhoun, B., “Using island-style bi-directional intra-CLB routing in low-power FPGAs”, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.
H. Qi, Ayorinde, O., and Calhoun, B. H., “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
B. H. Calhoun and Wentzloff, D. D., “Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT”, in HOT Chips, 2015.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., “An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches”, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
A. Banerjee and Calhoun, B. H., “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS”, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS”, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics”, in Proc. of GOMAC Tech, 2007.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics”, in Proc. of GOMAC Tech, 2007.
Y. Shakhsheer, Shrivastava, A., Roberts, N., Craig, K., Wooters, S., Wentzloff, D. D., and Calhoun, B. H., “Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors”, in GOMACTech, 2015.
Y. Shakhsheer, Shrivastava, A., Roberts, N., Craig, K., Wooters, S., Wentzloff, D. D., and Calhoun, B. H., “Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors”, in GOMACTech, 2015.
A. Banerjee and Calhoun, B. H., “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.
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J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs”, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.
P. Long, Huang, J. Z., Povolotskyi, M., Verreck, D., Charles, J., Kubis, T., Klimeck, G., Rodwell, M. J. W., and Calhoun, B. H., “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
P. Long, Huang, J. Z., Povolotskyi, M., Verreck, D., Charles, J., Kubis, T., Klimeck, G., Rodwell, M. J. W., and Calhoun, B. H., “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.

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