Robust Low Power VLSI

VLSI Design Group

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J. Wang and Calhoun, B. H., “Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.

P. Wang, Agarwala, R., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., “A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.

J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array”, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.

J. Wang and Calhoun, B. H., “Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM”, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.

J. Wang and Calhoun, B. H., “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs”, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.

J. Wang and Calhoun, B. H., “Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations”, Transactions on VLSI Systems (TVLSI), 2011.

L. Wang, Skadron, K., and Calhoun, B. H., “Dark vs. Dim Silicon and Near-Threshold Computing”, in Dark Silicon Workshop (DaSi), 2012.

D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.

S. N. Wooters, Calhoun, B. H., and Blalock, T. N., “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.

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F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things”, Journal of Low Power Electronics & Applications, 2018.

F. Yahya, Patel, H., Boley, J., Banerjee, A., and Calhoun, B. H., “A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.

F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.

F. B. Yahya, Patel, H. N., Chandra, V., and Calhoun, B. H., “Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation”, in 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 2015.

F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.

Y. Yu, Huang, J., Khanna, S., Calhoun, B. H., Lach, J., Shelat, A., and Evans, D., “A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm”. 2011 Workshop on RFID Security, 2011.

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F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.

L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR”, in IEEE Custom Integrated Circuits Conference (CICC), 2023.

Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., “Energy Efficient Design for Body Sensor Nodes”, Journal of Low Power Electronics and Applications, 2011.

L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.

Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.

Y. Zhang and Calhoun, B. H., “The Cost of Fixing Hold Time Violations in Sub-threshold Circuits”. 2011.

Y. Zhang and Calhoun, B. H., “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.

Y. Zhang and Calhoun, B. H., “Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits”, in International Symposium on Quality Electronic Design (ISQED), 2014.

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