Publications
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] Filters: First Letter Of Last Name is C and Author is B. H. Calhoun [Clear All Filters]
, “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.
, “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.
, “REESES: Rapid Efficient Energy Scalable ElectronicS”, in GOMAC Tech, 2010.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.
, “Body Area Sensor Networks: Challenges and Opportunities”, Computer, vol. 42, pp. 58–65, 2009.
, “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization”, in TECHCON, 2009.
, “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.