Robust Low Power VLSI

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J. Boley, Beshay, P., and Calhoun, B. H., “Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization”, Transactions of Very Large Scale Integration Systems, 2015.

J. Boley, Beshay, P., and Calhoun, B., “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.

J. Boley, Chandra, V., Aitken, R., and Calhoun, B., “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.