Robust Low Power VLSI
VLSI Design Group

Navigation

Search This Site

Publications

Conference Paper
S. Li, Liu, X., and Calhoun, B. H., “A 956pW Switched-Capacitor Sub-Bandgap Reference with 0.44-to-3.3V Supply Range, -67dB PSRR, and 0.2% within-Wafer Inaccuracy for Nanowatt IoT Systems”, in 2022 IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.
J. F. Ryan, Khanna, S., and Calhoun, B. H., “An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal”, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
J. F. Ryan, Wang, J., and Calhoun, B. H., “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.
J. Wang, Nalam, S., and Calhoun, B. H., “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
B. H. Calhoun and Chandrakasan, A., “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS”, in European Solid-State Circuits Conference, 2005, pp. 363-366.
H. L. Bishop, Wang, P., and Calhoun, B. H., “Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems”, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.
S. Nalam and Calhoun, B. H., “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.
S. Z. Ahmed, Tan, Y., Truesdell, D. S., and Ghosh, A., “Auger Effect Limited Performance in Tunnel Field Effect Transistors”, in 5th Berkeley Symposium on Energy Efficient Electronics & Steep Transistors Workshop, Berkeley, CA, 2017.
S. Kamineni, Sharma, A., Harjani, R., Sapatnekar, S. S., and Calhoun, B. H., “AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells”, in Design, Automation and Test in Europe Conference (DATE), 2023, 2023.PDF icon AuxcellGen-A Framework for Autonomous Generation of Analog and Memory Unit Cells.pdf (3.37 MB)
F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
W. C. Eberhardt, Shakhsheer, Y. A., and Calhoun, B. H., “A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability”, in IEEE Sensors, Limrick, Ireland, 2011.
J. Wang and Calhoun, B. H., “Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM”, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.
J. B. Stocking, Eberhardt, W. C., Shakhsheer, Y. A., Paulus, J. R., Appleby, M., and Calhoun, B. H., “A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing”, in IEEE Sensors, 2010.
D. S. Truesdell and Calhoun, B. H., “Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
B. H. Calhoun and Chandrakasan, A., “Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits”, in International Symposium on Low Power Electronics and Design, 2004, pp. 90-95.
A. Shrivastava, Lach, J., and Calhoun, B., “A Charge Pump Based Receiver Circuit for a Voltage Scaled Interconnect”, in International Symposium on Low Power Electronics and Design, 2012.
F. B. Yahya, Patel, H. N., Chandra, V., and Calhoun, B. H., “Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation”, in 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 2015.
A. Alghaihab, Chen, X., Shi, Y., Truesdell, D. S., Calhoun, B. H., and Wentzloff, D. D., “A Crystal-Less BLE Transmitter with -86dBm Frequency-Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
L. Wang, Skadron, K., and Calhoun, B. H., “Dark vs. Dim Silicon and Near-Threshold Computing”, in Dark Silicon Workshop (DaSi), 2012.
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., “Design Methodology for Fine-Grained Leakage Control in MTCMOS”, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
N. Liu and Calhoun, B. H., “Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
B. H. Calhoun, Wang, A., and Chandrakasan, A., “Device Sizing for Minimum Energy Operation in Subthreshold Circuits”, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.

Pages