Robust Low Power VLSI
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T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
H. Qi, Ayorinde, O., Huang, Y., and Calhoun, B., “Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs”, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, 2015.
H. Patel, Yahya, F., and Calhoun, B., “Optimizing SRAM Bitcell Reliability and Energy for IoT Applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.