Publications
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Author Title Type [ Year] Filters: First Letter Of Title is A and Author is B. H. Calhoun [Clear All Filters]
“Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN”, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.
, “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.
, “An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal”, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
, , “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.
, “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.
, “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
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