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B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
A. Banerjee and Calhoun, B. H., An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
B. H. Calhoun and Wentzloff, D. D., Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT, in HOT Chips, 2015.
H. Qi, Ayorinde, O., and Calhoun, B. H., An Ultra-Low-Power FPGA for IoT Applications, in S3S 2017, 2017.
O. Ayorinde, Qi, H., Huang, Y., and Calhoun, B., Using island-style bi-directional intra-CLB routing in low-power FPGAs, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.
A. Mallick, Bashar, M. K., Truesdell, D. S., Calhoun, B. H., Joshi, S., and Shukla, N., Using synchronized oscillators to compute the maximum independent set, Nature Communications, 2020.

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