Publications
Export 32 results:
Author Title [ Type
] Year Filters: Author is Daniel S. Truesdell [Clear All Filters]
, “A comprehensive analysis of Auger generation impacted planar Tunnel FETs”, Solid-State Electronics, 2020.
, “A Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packets”, IEEE Journal of Solid-State Circuits, 2021.
, “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB), “Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance”, Journal of Applied Physics, 2018.
, “A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range”, IEEE Solid-State Circuits Letters (SSCL), 2020. A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB), “Using synchronized oscillators to compute the maximum independent set”, Nature Communications, 2020.