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Author Title [ Type(Desc)] Year
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Conference Paper
A. Banerjee and Calhoun, B. H., An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell, in S3S, Monterey, CA, 2013.
Y. Shakhsheer, Shrivastava, A., Roberts, N., Craig, K., Wooters, S., Wentzloff, D. D., and Calhoun, B. H., Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors, in GOMACTech, 2015.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., Ultra-Dynamic Voltage Scaling for Energy Starved Electronics, in Proc. of GOMAC Tech, 2007.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
B. H. Calhoun and Wentzloff, D. D., Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT, in HOT Chips, 2015.
H. Qi, Ayorinde, O., and Calhoun, B. H., An Ultra-Low-Power FPGA for IoT Applications, in S3S 2017, 2017.
O. Ayorinde, Qi, H., Huang, Y., and Calhoun, B., Using island-style bi-directional intra-CLB routing in low-power FPGAs, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.