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S. Nalam, Chandra, V., Aitken, R. C., and Calhoun, B. H., “Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM”, in Design Automation and Test Europe (DATE), 2011.

S. Nalam, Bhargava, M., Mai, K., and Calhoun, B. H., “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.

S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.

S. Nalam and Calhoun, B. H., “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.

S. Nalam, Bhargava, M., Ringgenberg, K., Mai, K., and Calhoun, B. H., “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.