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Advanced Power distribution methods and their effects on the on-chip power network

Aggressive scaling according to Moore’s Law, combined with the push to incorporate more functionality and higher performance on a single chip, has created the widely known power problem in modern ICs. Power consumption has become a major limiting factor in many designs. A number of solutions have been preliminarily explored to help improve the energy efficiency of chips, including clock gating, power gating, local voltage regulation, and dynamic voltage scaling. While theoretical benefits of these techniques are known, their full impact on the overall power distribution network remains uncertain. This project aims to address the impact of Panoptic Dynamic Voltage Scaling (PDVS) on the power distribution network and compare them against alternative low power techniques.

Commercially available CAD tools and spice simulations will be used to synthesize and verify the power distribution network. A simplified model of the PDVS architecture with the power distribution network is given below. In this model the power distribution network is simplified to a RLC network, and the PDVS architecture is shown to have local distributed RC on the virtual VDD rails. Although simplified this model demonstrates the need to understand the full impact of PDVS on the power distribution network to know the true benefits that can be achieved. Information on the PDVS project can be found here.

In the context of power delivery characterization, we have closely examined structures like decoupling capacitors and power gating transistors. We have developed several interesting approaches for optimizing power gates for sub-threshold operation, to reduce switching noise on the supply rails, and to act as crude local DC-DC regulators. Faculty: Ben Calhoun Students: Kyle Craig Industry: Advanced Micro Devices (AMD)

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