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180nm Fully Depleted SOI for Sub-Vt SRAM cell and Device Characterization (chip 1 "thin chip")

This chip is designed with FDSOI 180nm technology rules and it's purpose is to build and verify characterization macros to support exploratory SRAM and sub-Vt designs. The set of infrastructure circuits have been verified and provide a means to extract the following types of information: 1) the device characteristics, explore the effect of back bias and drain bias on threshold voltage, 2) Vt mismatch for both NMOS and PMOS devices to determine the technology Avt value, 3) obtain the butterfly curves of various SRAM cell options designed for low power, 4) measure the read current for a range of bit cell designs and 5) examine the array leakage for various low power bit cell designs.